config.inc

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;------------------------------------------------------------------------------
;  This file defines the Monitor Configuration Parameters
;  Copyright KEIL ELEKTRONIK GmbH 1993 - 1999
;  Version 4.00
;------------------------------------------------------------------------------
;
; Definitions of Monitor Parameters
; ---------------------------------
;
; DATA_START: Defines the Start Address for the Monitor Data Area
;             Monitor uses 512 Bytes RAM starting at this location.
%DEFINE (DATA_START) (03A600H)     ; default Monitor data area 0xA600 .. 0xA7FF
;
; CODE_START: Defines the Start Address for the Monitor Code Area
;             Monitor requires 6KB for program code starting at this location.
%DEFINE (CODE_START) (03A800H)     ; default Monitor code area 0xA800 .. 0xBFFF
;
; VECTAB: Defines the Interrupt Vector Address relocation 
; Notes: This setting is ONLY relevant, if CODE_START is 0.  Locate interrupts
;        in your target application to the same address with uVision2
;        Project-Options for Target-L166 Misc-Interrupt Vector Table Address
;        (generates the L166 VECTAB directive).
%DEFINE (VECTAB) (08000H)         ; default Address 0x8000
;
; BAUDRATE: Defines the communication Baudrate for NON-BOOTSTRAP Mode.
; Notes: For SIMULATED SERIAL MODE the max. Baudrate is 38400bps @20MHz Clock.
;        Use the default baudrate first, before you check higher baudrates.
;        This setting is not relevant when you are using BOOTSTRAP Mode.
;        You may set BAUDRATE to 0 to enable automatic baudrate detection.
;        Automatic baudrate detection does not work for the SIMULATED SERIAL MODE.
BAUDRATE     EQU   9600     ; default Baudrate is 9600 bps.
;
; CPU_CLOCK: Defines the internal CPU Clock frequency
; Notes: The internal Clock might be different from the XTAL frequency, due
;        to on-chip PLL.  This setting is not relevant for BOOTSTRAP Mode.
CPU_CLOCK    EQU   20000000 ; default clock for most chips is 20MHz
;
;------------------------------------------------------------------------------
;
; Definitions for SYSCON Register (System Configuration):
; -------------------------------------------------------
;
; MCTC: Memory Cycle Time (SYSCON.0 .. SYSCON.3):
; Note: if RDYEN == 1 a maximum number of 7 waitstates can be selected
_MCTC   EQU     1       ; Memory wait states is 1 (MCTC = 0EH).
;                       ; (Reset Value = 15 additional state times)
;
; RWDC: Read/Write Signal Delay (SYSCON.4):
_RWDC   EQU     0       ; 0 = Delay Time     0.5 States (Reset Value)  
;                       ; 1 = No Delay Time  0   States
;
; MTTC: Memory Tri-state Time (SYSCON.5):
_MTTC   EQU     0       ; 0 = Delay Time     0.5 States (Reset Value)
;                       ; 1 = No Delay Time  0   States
;
; BTYP_ENABLE: Enable External Bus Configuration Control Bits
; --- Set BTYP_ENABLE = 1 to allow modification of BTYP and BUSACT field
;                         in the SYSCON register.
$SET (BTYP_ENABLE = 0)
;
; BTYP: External Bus Configuration Control (SYSCON.7 .. SYSCON.6):
; Note: These bits are only valid if _BUSACT == 1.
_BTYP   EQU     3       ; 0 = 8 Bit Non Multiplexed
;                       ; 1 = 8 Bit Multiplexed
;                       ; 2 = 16 Bit Multiplexed
;                       ; 3 = 16 Bit Non Multiplexed
;
; CLKEN: System Clock Output Enable bit (SYSCON.8):
_CLKEN  EQU     0       ; 0 = disabled    (Reset Value)
;                       ; 1 = enabled
;
; BYTDIS: Byte High Enable pin control bit (SYSCON.9):
_BYTDIS EQU     0       ; 0 = enabled     (Reset Value)
;                       ; 1 = disabled
;
; BUSACT: Bus Active Control Bit (SYSCON.10):
_BUSACT EQU     1       ; 0 = disabled
;                       ; 1 = enabled     (Reset Value)
;
; SGTDIS: Segmentation Disable control bit (SYSCON.11):
_SGTDIS EQU     0       ; 0 = enable segmented mode (Reset Value)
;                       ; 1 = disable segmented mode
;
; RDYEN: READY# Input Enable control bit (SYSCON.12):
_RDYEN  EQU     0       ; 0 = disabled    (Reset Value)
;                       ; 1 = enabled
;
; RDY_AS: Synchronous / Asynchronous READY# Input (SYSCON.3):
; Note: This bit is only valid if _RDYEN == 1.
_RDY_AS EQU     0       ; 0 = synchronous READY# input
;                       ; 1 = asynchronous READY# input
;
; STKSZ: Maximum System Stack Size selection  (SYSCON.13 .. SYSCON.14)
_STKSZ  EQU     0       ; System stack sizes
;                       ; 0 = 256 words (Reset Value)
;                       ; 1 = 128 words
;                       ; 2 =  64 words
;                       ; 3 =  32 words
;
;-----------------------------------------------------------------------------
;
; BUSCON1/ADDRSEL1 Initialization
; ===============================
;
;
; BUSCON1/ADDRSEL1
; --- Set BUSCON1 = 1 to initialize the BUSCON1/ADDRSEL1 registers
$SET (BUSCON1 = 0)
;
; Define the start address and the address range.  
; These values are used to set the ADDRSEL1 register
%DEFINE (ADDRESS1) (20000H)      ; Set CS1# Start Address (default 20000H)
%DEFINE (RANGE1)   (128K)        ; Set CS1# Range (default 128K)
;  
; MCTC1: Memory Cycle Time (BUSCON1.0 .. BUSCON1.3):
; Note: if RDYEN1 == 1 a maximum number of 7 waitstates can be selected
_MCTC1	 EQU	1	; Memory wait states is 1 (MCTC1 field = 0EH).
;
; RWDC1: Read/Write Signal Delay (BUSCON1.4):
_RWDC1	 EQU	0	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; MTTC1: Memory Tri-state Time (BUSCON1.5):
_MTTC1	 EQU	1	; 0 = Delay Time     0.5 States
;			; 1 = No Delay Time  0   States
;
; BTYP1: External Bus Configuration Control (BUSCON1.6 .. BUSCON1.7):
_BTYP1	 EQU	2	; 0 = 8 Bit Non Multiplexed
;			; 1 = 8 Bit Multiplexed
;			; 2 = 16 Bit Multiplexed
;			; 3 = 16 Bit Non Multiplexed
;
; ALECTL1: ALE Lengthening Control Bit (BUSCON1.9):
_ALECTL1 EQU	0	; see data sheet for description
;
; BUSACT1: Bus Active Control Bit (BUSCON1.10):
_BUSACT1 EQU	1	; = 0 external (ADDRSEL1) bus disabled
			; = 1 external (ADDRSEL1) bus enabled
;
; RDYEN1: READY# Input Enable control bit (BUSCON1.12):
_RDYEN1  EQU	0	; 0 = READY# function disabled
;			; 1 = READY# function enabled
;
;------------------------------------------------------------------------------