📄 syslib.c
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* Then use l(), lkAddr, ti(), and tt() to find the NULL access. * Defining _WRS_BSP_DEBUG_NULL_ACCESS adds an entry to the front * of the sysPhysMemDesc[] array. Any code which alters this table * will need adjustment (for example: sysPhysMemTop() is altered * to account for another entry into the sysPhysMemDesc[] array * when _WRS_BSP_DEBUG_NULL_ACCESS is defined. */ /* lower memory for invalid access */ { (VIRT_ADDR) 0x0, (PHYS_ADDR) 0x0, _WRS_BSP_VM_PAGE_OFFSET,# ifdef _WRS_BSP_DEBUG_NULL_ACCESS VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE, VM_STATE_VALID_NOT | VM_STATE_WRITABLE_NOT | VM_STATE_CACHEABLE_NOT# else VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_OS# endif /* _WRS_BSP_DEBUG_NULL_ACCESS */ }, /* lower memory for valid access */ { (VIRT_ADDR) _WRS_BSP_VM_PAGE_OFFSET, (PHYS_ADDR) _WRS_BSP_VM_PAGE_OFFSET, 0xa0000 - _WRS_BSP_VM_PAGE_OFFSET, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_OS }, /* video ram, etc */ { (VIRT_ADDR) 0x000a0000, (PHYS_ADDR) 0x000a0000, 0x00060000, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_IO },# if (LOCAL_MEM_LOCAL_ADRS >= 0x00100000) /* upper memory for OS */ { (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS, (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS, LOCAL_MEM_SIZE_OS, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_OS }, /* upper memory for Application */ { (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE_OS, (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE_OS, LOCAL_MEM_SIZE - LOCAL_MEM_SIZE_OS, /* it is changed in sysMemTop() */ VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_APPLICATION },# else /* LOCAL_MEM_LOCAL_ADRS is 0x0 */ /* upper memory for OS */ { (VIRT_ADDR) 0x00100000, (PHYS_ADDR) 0x00100000, LOCAL_MEM_SIZE_OS, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_OS }, /* upper memory for Application */ { (VIRT_ADDR) 0x00100000 + LOCAL_MEM_SIZE_OS, (PHYS_ADDR) 0x00100000 + LOCAL_MEM_SIZE_OS, LOCAL_MEM_SIZE - (0x00100000 + LOCAL_MEM_SIZE_OS), /* sysMemTop() fix */ VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_APPLICATION },# endif /* (LOCAL_MEM_LOCAL_ADRS >= 0x00100000) */# if defined(INCLUDE_SM_NET) && (SM_MEM_ADRS != 0x0) /* upper memory for sm net/obj pool */ { (VIRT_ADDR) SM_MEM_ADRS, (PHYS_ADDR) SM_MEM_ADRS, SM_MEM_SIZE + SM_OBJ_MEM_SIZE, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_APPLICATION },# endif /* defined(INCLUDE_SM_NET) && (SM_MEM_ADRS != 0x0) */# ifdef INCLUDE_IACSFL { (VIRT_ADDR) 0xFFF80000, (PHYS_ADDR) 0xFFF80000, 0x00080000, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_APPLICATION },# endif /* INCLUDE_IACSFL */ #else /* VM_PAGE_SIZE is 2/4MB */ /* 1st 2/4MB: lower mem + video ram etc + sm pool + upper mem */ { (VIRT_ADDR) 0x0, (PHYS_ADDR) 0x0, VM_PAGE_SIZE, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_OS },# if (LOCAL_MEM_LOCAL_ADRS >= VM_PAGE_SIZE) /* 2nd 2/4MB: upper memory for OS */ { (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS, (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS, LOCAL_MEM_SIZE_OS, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_OS }, /* remaining 2/4MB pages: upper memory for Application */ { (VIRT_ADDR) LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE_OS, (PHYS_ADDR) LOCAL_MEM_LOCAL_ADRS + LOCAL_MEM_SIZE_OS, LOCAL_MEM_SIZE - LOCAL_MEM_SIZE_OS, /* it is changed in sysMemTop() */ VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_APPLICATION },# else /* LOCAL_MEM_LOCAL_ADRS is 0x0 */ /* 2nd 2/4MB: upper memory for OS */ { (VIRT_ADDR) VM_PAGE_SIZE, (PHYS_ADDR) VM_PAGE_SIZE, LOCAL_MEM_SIZE_OS, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_OS }, /* remaining 2/4MB pages: upper memory for Application */ { (VIRT_ADDR) VM_PAGE_SIZE + LOCAL_MEM_SIZE_OS, (PHYS_ADDR) VM_PAGE_SIZE + LOCAL_MEM_SIZE_OS, LOCAL_MEM_SIZE - (VM_PAGE_SIZE + LOCAL_MEM_SIZE_OS), /* sysMemTop() fix */ VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_MEM_APPLICATION },# endif /* (LOCAL_MEM_LOCAL_ADRS >= VM_PAGE_SIZE) */#endif /* (VM_PAGE_SIZE == PAGE_SIZE_4KB) */ /* entries for dynamic mappings - create sufficient entries */ DUMMY_MMU_ENTRY, DUMMY_MMU_ENTRY, DUMMY_MMU_ENTRY, DUMMY_MMU_ENTRY, DUMMY_MMU_ENTRY, DUMMY_MMU_ENTRY, DUMMY_MMU_ENTRY, DUMMY_MMU_ENTRY, };int sysPhysMemDescNumEnt; /* number Mmu entries to be mapped */#ifdef INCLUDE_PC_CONSOLEPC_CON_DEV pcConDv [N_VIRTUAL_CONSOLES] = { {{{{NULL}}}, FALSE, NULL, NULL}, {{{{NULL}}}, FALSE, NULL, NULL} };#endif /* INCLUDE_PC_CONSOLE */#ifdef INCLUDE_FDIMPORT STATUS usrFdConfig (int type, int drive, char *fileName);FD_TYPE fdTypes[] = { {2880,18,2,80,2,0x1b,0x54,0x00,0x0c,0x0f,0x02,1,1,"1.44M"}, {2400,15,2,80,2,0x24,0x50,0x00,0x0d,0x0f,0x02,1,1,"1.2M"}, };UINT sysFdBuf = FD_DMA_BUF_ADDR; /* floppy disk DMA buffer address */UINT sysFdBufSize = FD_DMA_BUF_SIZE; /* floppy disk DMA buffer size */#endif /* INCLUDE_FD */#ifdef INCLUDE_ATAIMPORT STATUS usrAtaConfig (int ctrl, int drive, char *fileName);ATA_TYPE ataTypes[ATA_MAX_CTRLS][ATA_MAX_DRIVES] = { /* controller zero */ { /* ctrl 0 drive 0 */ { ATA_CTRL0_DRV0_CYL, /* Number of cylinders on device */ ATA_CTRL0_DRV0_HDS, /* Number of heads on device */ ATA_CTRL0_DRV0_SPT, /* Number of sectors per track on device */ ATA_CTRL0_DRV0_BPS, /* Number of bytes per sector on device */ ATA_CTRL0_DRV0_WPC /* write precompensation 0xff = don't use */ }, /* ctrl 0 drive 1 */ { ATA_CTRL0_DRV1_CYL, /* Number of cylinders on device */ ATA_CTRL0_DRV1_HDS, /* Number of heads on device */ ATA_CTRL0_DRV1_SPT, /* Number of sectors per track on device */ ATA_CTRL0_DRV1_BPS, /* Number of bytes per sector on device */ ATA_CTRL0_DRV1_WPC /* write precompensation 0xff = don't use */ }, }, /* controller one */ { /* ctrl 1 drive 0 */ { ATA_CTRL1_DRV0_CYL, /* Number of cylinders on device */ ATA_CTRL1_DRV0_HDS, /* Number of heads on device */ ATA_CTRL1_DRV0_SPT, /* Number of sectors per track on device */ ATA_CTRL1_DRV0_BPS, /* Number of bytes per sector on device */ ATA_CTRL1_DRV0_WPC /* write precompensation 0xff = don't use */ }, /* ctrl 1 drive 1 */ { ATA_CTRL1_DRV1_CYL, /* Number of cylinders on device */ ATA_CTRL1_DRV1_HDS, /* Number of heads on device */ ATA_CTRL1_DRV1_SPT, /* Number of sectors per track on device */ ATA_CTRL1_DRV1_BPS, /* Number of bytes per sector on device */ ATA_CTRL1_DRV1_WPC /* write precompensation 0xff = don't use */ } } };ATA_RESOURCE ataResources[ATA_MAX_CTRLS] = { /* ATA controller zero resources */ { /* PCCARD_RESOURCE */ { ATA0_VCC, /* 3-5 volts Vcc */ ATA0_VPP, /* 5-12 volts Vpp */ { ATA0_IO_START0, /* start I/O address 0 */ ATA0_IO_START1 /* start I/O address 1 */ }, { ATA0_IO_STOP0, /* end I/0 address 0 */ ATA0_IO_STOP1 /* end I/0 address 1 */ }, ATA0_EXTRA_WAITS, /* extra wait states 0-2 */ ATA0_MEM_START, /* start host mem address */ ATA0_MEM_STOP, /* stop host mem address */ ATA0_MEM_WAITS, /* mem extra wait states 0-2 */ ATA0_MEM_OFFSET, /* mem offset of card address */ ATA0_MEM_LENGTH /* length of memory */ }, ATA0_CTRL_TYPE, /* IDE_LOCAL or ATA_PCMCIA */ ATA0_NUM_DRIVES, /* number of drives on controller */ INT_NUM_ATA0, /* interrupt number of controller */ ATA0_INT_LVL, /* interrupt level of controller */ ATA0_CONFIG, /* device configuration settings */ ATA0_SEM_TIMEOUT, /* semaphore timeout for controller */ ATA0_WDG_TIMEOUT, /* watchdog timeout for controller */ ATA0_SOCKET_TWIN, /* socket number for twin card */ ATA0_POWER_DOWN /* power down mode for this controller */ }, /* ctrl 0 end */ /* ATA controller one resources */ { /* PCCARD_RESOURCE */ { ATA1_VCC, /* 3-5 volts Vcc */ ATA1_VPP, /* 5-12 volts Vpp */ { ATA1_IO_START0, /* start I/O address 0 */ ATA1_IO_START1 /* start I/O address 1 */ }, { ATA1_IO_STOP0, /* end I/0 address 0 */ ATA1_IO_STOP1 /* end I/0 address 1 */ }, ATA1_EXTRA_WAITS, /* extra wait states 0-2 */ ATA1_MEM_START, /* start host mem address */ ATA1_MEM_STOP, /* stop host mem address */ ATA1_MEM_WAITS, /* mem extra wait states 0-2 */ ATA1_MEM_OFFSET, /* mem offset of card address */ ATA1_MEM_LENGTH /* length of memory */ }, ATA1_CTRL_TYPE, /* IDE_LOCAL or ATA_PCMCIA */ ATA1_NUM_DRIVES, /* number of drives on controller */ INT_NUM_ATA1, /* interrupt number of controller */ ATA1_INT_LVL, /* interrupt level of controller */ ATA1_CONFIG, /* device configuration settings */ ATA1_SEM_TIMEOUT, /* semaphore timeout for controller */ ATA1_WDG_TIMEOUT, /* watchdog timeout for controller */ ATA1_SOCKET_TWIN, /* socket number for twin card */ ATA1_POWER_DOWN /* power down mode for this controller */ } /* ctrl 1 end */ };#endif /* INCLUDE_ATA */#ifdef INCLUDE_LPTLPT_RESOURCE lptResources [N_LPT_CHANNELS] = { {LPT0_BASE_ADRS, INT_NUM_LPT0, LPT0_INT_LVL, TRUE, 10000, 10000, 1, 1, 0 }, {LPT1_BASE_ADRS, INT_NUM_LPT1, LPT1_INT_LVL, TRUE, 10000, 10000, 1, 1, 0 }, {LPT2_BASE_ADRS, INT_NUM_LPT2, LPT2_INT_LVL, TRUE, 10000, 10000, 1, 1, 0 } };#endif /* INCLUDE_LPT */int sysBus = BUS; /* system bus type (VME_BUS, etc) */int sysCpu = CPU; /* system cpu type (MC680x0) */char *sysBootLine = BOOT_LINE_ADRS; /* address of boot line */char *sysExcMsg = EXC_MSG_ADRS; /* catastrophic message area */int sysProcNum; /* processor number of this cpu */int sysFlags; /* boot flags */char sysBootHost [BOOT_FIELD_LEN]; /* name of host from which we booted */char sysBootFile [BOOT_FIELD_LEN]; /* name of file from which we booted */UINT sysIntIdtType = SYS_INT_TRAPGATE; /* IDT entry type */UINT sysProcessor = (UINT) NONE; /* 0=386, 1=486, 2=P5, 4=P6, 5=P7 */UINT sysCoprocessor = 0; /* 0=none, 1=387, 2=487 */int sysWarmType = SYS_WARM_TYPE; /* system warm boot type */int sysWarmFdDrive = SYS_WARM_FD_DRIVE; /* 0 = drive a:, 1 = b: */int sysWarmFdType = SYS_WARM_FD_TYPE; /* 0 = 3.5" 2HD, 1 = 5.25" 2HD */int sysWarmAtaCtrl = SYS_WARM_ATA_CTRL; /* controller 0 or 1 */int sysWarmAtaDrive = SYS_WARM_ATA_DRIVE; /* Hd drive 0 (c:), 1 (d:) */int sysWarmTffsDrive= SYS_WARM_TFFS_DRIVE; /* TFFS drive 0 (DOC) */UINT sysStrayIntCount = 0; /* Stray interrupt count */char *memTopPhys = NULL; /* top of memory */char *memRom = NULL; /* saved bootrom image */
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