hwconf.c

For WorkBench2.31 的pentium4 BSP

/* hwconf.c - Hardware configuration support module */


/* Copyright (c) 2005 Wind River Systems, Inc. */

/*
modification history
--------------------
01u,29sep05,mdo  Fix gnu warnings
*/

 
/* includes */
 
#include <vxWorks.h>
#include <vxBusLib.h>
#include <hwif/vxbus/busLib.h>
#include <hwif/vxbus/plbBusLib.h>
#include <hwif/vxbus/pciBusLib.h>
#include <hwif/vxbus/hwConf.h>
#include "config.h"

extern void plbRegister(void);
extern void pentiumPciRegister(void);
extern void pciSlotRegister(void);

struct plbDevEntry      sysPlbDevTable[] =
    {
    { (void *)0xDEC80000, "pentiumPci", 0, NULL, NULL },
    { (void *)0xE8001FF8, "d1643rtc", 0, NULL, NULL },
    { (void *)0, "", 0, NULL, NULL },
    };

int                     sysPlbDevTableNumEntries = NELEMENTS(sysPlbDevTable);

#define TEST_POOL_SIZE 50000
char busTestPool[TEST_POOL_SIZE];

/* vxBus resource files for onboard UARTS */

const struct hcfResource pentiumi82501Resources[] =
    {
        { "regBase",     HCF_RES_INT, {(void *)COM1_BASE_ADR} },
        { "irq",         HCF_RES_INT, {(void *)(INUM_TO_IVEC(INT_NUM_COM1))} },
        { "regInterval", HCF_RES_INT, {(void *)UART_REG_ADDR_INTERVAL} },
        { "irqLevel",    HCF_RES_INT, {(void *)COM1_INT_LVL} },
    };
#define pentiumi82501Num NELEMENTS(pentiumi82501Resources)

const struct hcfResource pentiumi82502Resources[] =
    {
        { "regBase",     HCF_RES_INT, {(void *)COM2_BASE_ADR} },
        { "irq",         HCF_RES_INT, {(void *)(INUM_TO_IVEC(INT_NUM_COM2))} },
        { "regInterval", HCF_RES_INT, {(void *)UART_REG_ADDR_INTERVAL} },
        { "irqLevel",    HCF_RES_INT, {(void *)COM2_INT_LVL} },
    };
#define pentiumi82502Num NELEMENTS(pentiumi82502Resources)

const struct hcfResource pentiumPci0Resources[] = {
    { "regBase", HCF_RES_INT, {(void *)0x00} }
};
#define pentiumPci0Num NELEMENTS(pentiumPci0Resources)

const struct hcfResource pciSlot0Resources[] = {
    { "label",  HCF_RES_INT, {(void *)"slot 1"} },
    { "hose",   HCF_RES_INT, {(void *)0} },
    { "bus",    HCF_RES_INT, {(void *)5} },
    { "device", HCF_RES_INT, {(void *)2} },
    { "intr0",  HCF_RES_INT, {(void *)0} },
    { "intr1",  HCF_RES_INT, {(void *)0} },
    { "intr2",  HCF_RES_INT, {(void *)0} },
    { "intr3",  HCF_RES_INT, {(void *)0} }
};
#define pciSlot0Num NELEMENTS(pciSlot0Resources)


const struct hcfResource pciSlot5Resources[] = {
    { "label",  HCF_RES_INT, {(void *)"slot 5"} },
    { "hose",   HCF_RES_INT, {(void *)0} },
    { "bus",    HCF_RES_INT, {(void *)3} },
    { "device", HCF_RES_INT, {(void *)1} },
    { "intr0",  HCF_RES_INT, {(void *)0} },
    { "intr1",  HCF_RES_INT, {(void *)0} },
    { "intr2",  HCF_RES_INT, {(void *)0} },
    { "intr3",  HCF_RES_INT, {(void *)0} }
};
#define pciSlot5Num NELEMENTS(pciSlot5Resources)

const struct hcfDevice hcfDeviceList[] = {
    { "ns16550", 1, VXB_BUSID_PLB, 0, pentiumi82502Num, pentiumi82502Resources },
    { "ns16550", 0, VXB_BUSID_PLB, 0, pentiumi82501Num, pentiumi82501Resources },
    { "pentiumPci", 0, VXB_BUSID_NEXUS, 0, pentiumPci0Num, pentiumPci0Resources },
    { "pciSlot", 0, VXB_BUSID_PCI,  0, pciSlot0Num, pciSlot0Resources },
    { "pciSlot", 0, VXB_BUSID_PCIX, 0, pciSlot5Num, pciSlot5Resources },
};
const int hcfDeviceNum = NELEMENTS(hcfDeviceList);