📄 startup.s
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IF (EIC_SETUP != 0)
// Import IRQ Handlers
EXTERN CODE32 (T0TIMIIRQHandler)
EXTERN CODE32 (FLASHIRQHandler)
EXTERN CODE32 (RCCUIRQHandler)
EXTERN CODE32 (RTCIRQHandler)
EXTERN CODE32 (WDGIRQHandler)
EXTERN CODE32 (XTIIRQHandler)
EXTERN CODE32 (USBHPIRQHandler)
EXTERN CODE32 (I2C0ITERRIRQHandler)
EXTERN CODE32 (I2C1ITERRIRQHandler)
EXTERN CODE32 (UART0IRQHandler)
EXTERN CODE32 (UART1IRQHandler)
EXTERN CODE32 (UART2IRQHandler)
EXTERN CODE32 (UART3IRQHandler)
EXTERN CODE32 (BSPI0IRQHandler)
EXTERN CODE32 (BSPI1IRQHandler)
EXTERN CODE32 (I2C0IRQHandler)
EXTERN CODE32 (I2C1IRQHandler)
EXTERN CODE32 (CANIRQHandler)
EXTERN CODE32 (ADC12IRQHandler)
EXTERN CODE32 (T1TIMIIRQHandler)
EXTERN CODE32 (T2TIMIIRQHandler)
EXTERN CODE32 (T3TIMIIRQHandler)
EXTERN CODE32 (HDLCIRQHandler)
EXTERN CODE32 (USBLPIRQHandler)
EXTERN CODE32 (T0TOIIRQHandler)
EXTERN CODE32 (T0OC1IRQHandler)
EXTERN CODE32 (T0OC2IRQHandler)
// Peripherals IRQ Handlers Address Table
PUBLIC IRQ_Vectors
IRQ_Vectors:
T0TIMI_Addr: DD T0TIMIIRQHandler
FLASH_Addr: DD FLASHIRQHandler
RCCU_Addr: DD RCCUIRQHandler
RTC_Addr: DD RTCIRQHandler
WDG_Addr: DD WDGIRQHandler
XTI_Addr: DD XTIIRQHandler
USBHP_Addr: DD USBHPIRQHandler
I2C0ITERR_Addr: DD I2C0ITERRIRQHandler
I2C1ITERR_Addr: DD I2C1ITERRIRQHandler
UART0_Addr: DD UART0IRQHandler
UART1_Addr: DD UART1IRQHandler
UART2_Addr: DD UART2IRQHandler
UART3_Addr: DD UART3IRQHandler
BSPI0_Addr: DD BSPI0IRQHandler
BSPI1_Addr: DD BSPI1IRQHandler
I2C0_Addr: DD I2C0IRQHandler
I2C1_Addr: DD I2C1IRQHandler
CAN_Addr: DD CANIRQHandler
ADC12_Addr: DD ADC12IRQHandler
T1TIMI_Addr: DD T1TIMIIRQHandler
T2TIMI_Addr: DD T2TIMIIRQHandler
T3TIMI_Addr: DD T3TIMIIRQHandler
DD 0 ; Reserved
DD 0 ; Reserved
DD 0 ; Reserved
HDLC_Addr: DD HDLCIRQHandler
USBLP_Addr: DD USBLPIRQHandler
DD 0 ; Reserved
DD 0 ; Reserved
T0TOI_Addr: DD T0TOIIRQHandler
T0OC1_Addr: DD T0OC1IRQHandler
T0OC2_Addr: DD T0OC2IRQHandler
ENDIF
// Reset Handler
Reset_Handler:
NOP ; Wait for OSC stabilization
NOP
NOP
NOP
NOP
NOP
NOP
NOP
IF (PERIPH_RESET != 0)
LDR R1, =APB1_BASE
LDR R2, =APB2_BASE
LDR R3, =APB1_Mask
LDR R4, =APB2_Mask
STRH R3, [R1, #CKDIS_OFS] ; Disable Clock for APB1 periph.
STRH R4, [R2, #CKDIS_OFS] ; Disable Clock for APB2 periph.
STRH R3, [R1, #SWRES_OFS] ; Keep under Reset APB1 periph.
STRH R4, [R2, #SWRES_OFS] ; Keep under Reset APB2 periph.
MOV R0, #10
PR_Loop1 SUBS R0, R0, #1 ; Wait that selected macrocells
BNE PR_Loop1 ; enter reset
STRH R0, [R1, #SWRES_OFS] ; Release Reset of APB1 periph.
STRH R0, [R2, #SWRES_OFS] ; Relase Reset of APB2 periph.
STRH R0, [R1, #CKDIS_OFS] ; Enable Clock for APB1 periph.
STRH R0, [R2, #CKDIS_OFS] ; Enable Clock for APB2 periph.
MOV R0, #10
PR_Loop2 SUBS R0, R0, #1 ; Wait that selected macrocells
BNE PR_Loop2 ; exit from reset
ENDIF
IF (EMI_SETUP != 0)
LDR R0, =GPIO2_BASE ; Configure P2.0..7 for Ext. Bus
LDR R1, [R0, #PC0_OFS]
ORR R1, R1, #0x0000000F
STR R1, [R0, #PC0_OFS]
LDR R1, [R0, #PC1_OFS]
ORR R1, R1, #0x0000000F
STR R1, [R0, #PC1_OFS]
LDR R1, [R0, #PC2_OFS]
ORR R1, R1, #0x0000000F
STR R1, [R0, #PC2_OFS]
LDR R0, =EMI_BASE ; Configure EMI
LDR R1, =BCON0_Val
STR R1, [R0, #BCON0_OFS]
LDR R1, =BCON1_Val
STR R1, [R0, #BCON1_OFS]
LDR R1, =BCON2_Val
STR R1, [R0, #BCON2_OFS]
LDR R1, =BCON3_Val
STR R1, [R0, #BCON3_OFS]
ENDIF
IF (EIC_SETUP != 0)
LDR R0, =EIC_BASE
LDR R1, =0xE59F0000 ; LDR PC,[PC,#ofs] (High 16-bits)
STR R1, [R0, #IVR_OFS] ; Store into IVR[31:16]
; LDR R1, =IRQ_Vectors ; IRQ Address Table
ADR R1, IRQ_Vectors ; IRQ Address Table
LDR R2, =0x0FFF ; Offset Mask
AND R1, R1, R2 ; Mask Offset
LDR R2, =0xF7E0 ; Jump Offset = 0x07E0
; 0xFXXX is used to complete the
; LDR PC,[PC,#ofs]
; 0x07E0 = 0x07E8 - 8 (Prefetch)
; 0 = IVR Address + 0x7E8
ADD R1, R1, R2 ; Add Jump Offset
MOV R2, #32 ; Number of Channels
MOV R3, #SIR0_OFS ; Offset to SIR0
EIC_Loop MOV R4, R1, LSL #16 ; Use High 16-bits
STR R4, [R0, R3] ; Store into SIRx
ADD R1, R1, #4 ; Next IRQ Address
ADD R3, R3, #4 ; Next SIRx
SUBS R2, R2, #1 ; Decrement Counter
BNE EIC_Loop
ENDIF
// Memory Remapping
BOOTCR EQU 0xA0000050 /* Boot Configuration Register */
FLASH_BM EQU 0x00 /* Boot Mode: Flash at 0 */
RAM_BM EQU 0x02 /* Boot Mode: RAM at 0 */
EXTMEM_BM EQU 0x03 /* Boot Mode: EXTMEM at 0 */
$IF (REMAP)
$IF (EXTMEM_MODE)
MOV R1, #EXTMEM_BM
$ELSEIF (RAM_MODE)
MOV R1, #RAM_BM
$ELSE
MOV R1, #FLASH_BM
$ENDIF
LDR R0, =BOOTCR
LDRH R2, [R0] ; Read BOOTCR
BIC R2, R2, #0x03 ; Clear two LSB bits
ORR R2, R2, R1 ; Setup two LSB bits
STRH R2, [R0] ; Write BOOTCR
$ENDIF
// Setup Stack for each mode
LDR R0, =Top_Stack
// Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
// Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
// Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
// Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
// Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
// Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
MOV SP, R0
// Enter the C code
LDR R0,=?C?INIT
TST R0,#1 ; Bit-0 set: INIT is Thumb
LDREQ LR,=exit?A ; ARM Mode
LDRNE LR,=exit?T ; Thumb Mode
BX R0
ENDP
PUBLIC exit?A
exit?A PROC CODE32
B exit?A
ENDP
PUBLIC exit?T
exit?T PROC CODE16
B exit?T
ENDP
END
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