startup.s

STMicroelectronics STR7xFxx A/D Example Program

/***********************************************************************/
/*  This file is part of the uVision/ARM development tools             */
/*  Copyright KEIL ELEKTRONIK GmbH 2002-2005                           */
/***********************************************************************/
/*                                                                     */
/*  STARTUP.S:  Startup file for ST STR71x device series               */
/*                                                                     */
/***********************************************************************/


/* 
//*** <<< Use Configuration Wizard in Context Menu >>> *** 
*/


/*
 *  The STARTUP.S code is executed after CPU Reset. This file may be 
 *  translated with the following SET symbols. In uVision these SET 
 *  symbols are entered under Options - ASM - Set.
 *
 *  REMAP: when set the startup code initializes the register BOOTCR 
 *  which overwrites the settings of the CPU configuration pins. The 
 *  startup and interrupt vectors are remapped from:
 *     0x40000000  default setting
 *     0x60000000  when EXTMEM_MODE is used
 *     0x20000000  when RAM_MODE is used
 *
 *  EXTMEM_MODE: when set the device is configured for code execution
 *  from external memory starting at address 0x60000000. The startup
 *  vectors are located to 0x60000000.
 *
 *  RAM_MODE: when set the device is configured for code execution
 *  from on-chip RAM starting at address 0x20000000. The startup
 *  vectors are located to 0x20000000.
 */


// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs

        Mode_USR  EQU      0x10
        Mode_FIQ  EQU      0x11
        Mode_IRQ  EQU      0x12
        Mode_SVC  EQU      0x13
        Mode_ABT  EQU      0x17
        Mode_UND  EQU      0x1B
        Mode_SYS  EQU      0x1F

        I_Bit     EQU      0x80    /* when I bit is set, IRQ is disabled */
        F_Bit     EQU      0x40    /* when F bit is set, FIQ is disabled */


/*
// <h> Stack Configuration (Stack Sizes in Bytes)
//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:4>
//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:4>
//   <o2> Abort Mode          <0x0-0xFFFFFFFF:4>
//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:4>
//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:4>
//   <o5> User/System Mode    <0x0-0xFFFFFFFF:4>
// </h>
*/
        UND_Stack_Size  EQU     0x00000004
        SVC_Stack_Size  EQU     0x00000004
        ABT_Stack_Size  EQU     0x00000004
        FIQ_Stack_Size  EQU     0x00000004
        IRQ_Stack_Size  EQU     0x00000400
        USR_Stack_Size  EQU     0x00000400

AREA   STACK, DATA, READWRITE, ALIGN=2
        DS   (USR_Stack_Size+3)&~3  ; Stack for User/System Mode 
        DS   (SVC_Stack_Size+3)&~3  ; Stack for Supervisor Mode
        DS   (IRQ_Stack_Size+3)&~3  ; Stack for Interrupt Mode
        DS   (FIQ_Stack_Size+3)&~3  ; Stack for Fast Interrupt Mode 
        DS   (ABT_Stack_Size+3)&~3  ; Stack for Abort Mode
        DS   (UND_Stack_Size+3)&~3  ; Stack for Undefined Mode
Top_Stack:


// APB Bridge 1 & 2 definitions (Peripherals)
        APB1_BASE       EQU     0xC0000000  /* APB Bridge 1 Base Address */
        APB2_BASE       EQU     0xE0000000  /* APB Bridge 2 Base Address */
        CKDIS_OFS       EQU     0x10        /* Clock Disable Register Offset */
        SWRES_OFS       EQU     0x14        /* Sowtware Reset Register Offset */
        APB1_Mask       EQU     0x27FB      /* APB1 Peripherals Mask */
        APB2_Mask       EQU     0x7FDD      /* APB2 Peripherals Mask */

/*
// <e> Reset all Device Peripherals
*/
        PERIPH_RESET    EQU     0
/*
// </e>
*/


// External Memory Interface (EMI) definitions
        EMI_BASE        EQU     0x6C000000  /* EMI Base Address */
        BCON0_OFS       EQU     0x00        /* BCON0 Offset */
        BCON1_OFS       EQU     0x04        /* BCON1 Offset */
        BCON2_OFS       EQU     0x08        /* BCON2 Offset */
        BCON3_OFS       EQU     0x0C        /* BCON3 Offset */

/*
// <e> External Memory Interface (EMI)
*/
        EMI_SETUP       EQU     0

/*
//   <h> Bank Configuration 0 (BCON0)
//     <o.15>    BE: Bank Enable
//     <o.0..1>  B_SIZE: Bus Size  <0=>  8-bit    <1=> 16-bit
//                                 <2=> Reserved  <3=> Reserved
//     <o.2..5>  C_LENGTH: Cycle Length <0-15>
//               <i> Number of Wait States
//   </h>
*/
        BCON0_Val       EQU     0x0000801D

/*
//   <h> Bank Configuration 1 (BCON1)
//     <o.15>    BE: Bank Enable
//     <o.0..1>  B_SIZE: Bus Size  <0=>  8-bit    <1=> 16-bit
//                                 <2=> Reserved  <3=> Reserved
//     <o.2..5>  C_LENGTH: Cycle Length <0-15>
//               <i> Number of Wait States
//   </h>
*/
        BCON1_Val       EQU     0x0000801D

/*
//   <h> Bank Configuration 2 (BCON2)
//     <o.15>    BE: Bank Enable
//     <o.0..1>  B_SIZE: Bus Size  <0=>  8-bit    <1=> 16-bit
//                                 <2=> Reserved  <3=> Reserved
//     <o.2..5>  C_LENGTH: Cycle Length <0-15>
//               <i> Number of Wait States
//   </h>
*/
        BCON2_Val       EQU     0x0000001D
        
/*
//   <h> Bank Configuration 3 (BCON3)
//     <o.15>    BE: Bank Enable
//     <o.0..1>  B_SIZE: Bus Size  <0=>  8-bit    <1=> 16-bit
//                                 <2=> Reserved  <3=> Reserved
//     <o.2..5>  C_LENGTH: Cycle Length <0-15>
//               <i> Number of Wait States
//   </h>
*/
        BCON3_Val       EQU     0x0000001D

/*
// </e> End of EMI
*/


// GPIO Port 2 definitions (for External Memory Interface setup)
        GPIO2_BASE      EQU     0xE0005000  /* GPIO2 Base Address */
        PC0_OFS         EQU     0x00        /* PC0 Offset */
        PC1_OFS         EQU     0x04        /* PC1 Offset */
        PC2_OFS         EQU     0x08        /* PC2 Offset */
        PD_OFS          EQU     0x0C        /* PD Offset */


// Enhanced Interrupt Controller (EIC) definitions
        EIC_BASE        EQU     0xFFFFF800  /* EIC Base Address */
        ICR_OFS         EQU     0x00        /* Interrupt Control Reg. Offset */
        CIPR_OFS        EQU     0x08        /* Curr. Int. Priority R. Offset */
        IVR_OFS         EQU     0x18        /* Interrupt Vector Reg. Offset */
        FIR_OFS         EQU     0x1C        /* Fast Interrupt Reg. Offset */
        IER_OFS         EQU     0x20        /* Interrupt Enable Reg. Offset */
        IPR_OFS         EQU     0x40        /* Interrupt Pending Reg. Offset */
        SIR0_OFS        EQU     0x60        /* Source Interrupt Reg. 0 Offset */

/*
// <e> Setup EIC and Exception Handlers
*/
        EIC_SETUP       EQU     0
/*
// </e>
*/


// Starupt Code must be linked first at Address at which it expects to run.

$IF     (EXTMEM_MODE)
        CODE_BASE       EQU     0x60000000
$ELSEIF (RAM_MODE)
        CODE_BASE       EQU     0x20000000
$ELSE
        CODE_BASE       EQU     0x40000000
$ENDIF

AREA   STARTUPCODE, CODE, AT CODE_BASE   // READONLY, ALIGN=4
       PUBLIC  __startup

       EXTERN  CODE32 (?C?INIT)

__startup       PROC    CODE32

// Pre-defined interrupt handlers that may be directly 
// overwritten by C interrupt functions
EXTERN CODE32 (Undef_Handler?A)
EXTERN CODE32 (SWI_Handler?A)
EXTERN CODE32 (PAbt_Handler?A)
EXTERN CODE32 (DAbt_Handler?A)
EXTERN CODE32 (IRQ_Handler?A)
EXTERN CODE32 (FIQ_Handler?A)

// Exception Vectors
// Mapped to Address 0.
// Absolute addressing mode must be used.

Vectors:        LDR     PC,Reset_Addr         
                LDR     PC,Undef_Addr
                LDR     PC,SWI_Addr
                LDR     PC,PAbt_Addr
                LDR     PC,DAbt_Addr
                NOP                         /* Reserved Vector */
IF (EIC_SETUP != 0)                
                LDR     PC,IRQ_Addr
ELSE
                LDR     PC,[PC, #-0x0808]   /* Vector from EIC_IVR */
ENDIF
                LDR     PC,FIQ_Addr

Reset_Addr:     DD      Reset_Handler
Undef_Addr:     DD      Undef_Handler?A
SWI_Addr:       DD      SWI_Handler?A
PAbt_Addr:      DD      PAbt_Handler?A
DAbt_Addr:      DD      DAbt_Handler?A
                DD      0                   /* Reserved Address */
IRQ_Addr:       DD      IRQ_Handler?A
FIQ_Addr:       DD      FIQ_Handler?A