siopcddl.h

VRTX 商用嵌入式实时操作系统

/***************************************************************************
*
*               Copyright (c) 1996 Microtec Research, Inc.
*
*       All rights reserved. MICROTEC RESEARCH's source code is an unpublished
*       work and the use of a copyright notice does not imply otherwise.
*       This source code contains confidential, trade secret material of
*       MICROTEC RESEARCH. Any attempt or participation in deciphering,
*       decoding, reverse engineering or in any way altering the source code
*       is strictly prohibited, unless the prior written consent of
*       MICROTEC RESEARCH is obtained.
*
*
*       Module Name:            siopcddl.h
*
*       Identification:         @(#) 1.1 siopcddl.h
*
*       Date:                   9/16/94  17:54:04
*
****************************************************************************
*/

/*
 * Include file for the Device Dependent Layer of the sio driver
 * for the 16550 UART for PC/AT
 */

/*
 * Misc. Defines
 */

#define SIO_NUM_ADAPTERS    1      /* Number of adapters */
#define SIOPC_MAX_PORTS     2      /* Number of ports : COM1, COM2, ... */
#define SIOPC_ADAPT_NUM     0      /* Only one adapter */
#define SIOPC_CLIST_SZ      128    /* Character list size */

typedef volatile unsigned char v_char;

typedef struct {
  u_short *clist;            /* Current message being received */
  u_short *cl_tail;
  u_short *cl_end;

  mblk_t *tx_msg;            /* Current message being transmitted */
  int    port;               /* Port Number for this port         */
  int    state;              /* State Info            */
  char   ss_char;            /* Start or Stop Char to Tx */

  struct swk_irq_req irqreq; /* Interrupt Request Structure */
  int intr_srv_sched;        /* Was the Interrupt Service Routine Scheduled */

  v_char *rx;                /* receive register */
  v_char *tx;                /* transmit register */
  v_char *ier;               /* interrupt enable */
  v_char *iir;               /* interrupt id */
  v_char *lcr;               /* line control */
  v_char *mcr;               /* modem control */
  v_char *lsr;               /* line status */
  v_char *msr;               /* modem status */
  v_char *dll;               /* divisor latch upper byte */
  v_char *dlm;               /* divisor latch lower byte */

#ifdef SIOPC_DEBUG
  int nb_it_err ;
  int nb_it_tx ;
  int nb_it_rx ;
  int nb_char_tx ;
  int last_err ;
  int nb_tot_its ;
#endif

  v_char *   base ;          /* Base address of port */
  int        irq ;           /* IRQ level of port */

  void       (*port_enable_intr)(_ANSIPROT1(void));
  int        (*port_disable_intr)(_ANSIPROT1(void));
  void       (*isr)(_ANSIPROT1(void));

} siopc_port_t;

/*
 * defines for state field of siopc_port_t struct
 */

#define SIOPC_SUS_OUT        0x00000001   /* Output Suspended */
#define SIOPC_CR_INSERT      0x00000002   /* CR inserted */
#define SIOPC_CR_NL          0x00000004   /* Map NL to CR-NL  */
#define SIOPC_TX_SS          0x00000008   /* Tx start or Stop Char */
#define SIOPC_OPEN           0x00000010   /* Port is open          */
#define SIOPC_RX_BREAK       0x00000020   /* received break is pending */
#define SIOPC_END_OF_TX      0x00000040   /* current character transmitted */

/*
 * Interrupt Vector
 */

#define PIC_M_LEVEL     0x30
#define IRQ_COM1        4
#define IRQ_COM2        3

/* 8259 interrupts */
/* --------------- */
#define PIC_M_MASK          0x21      /* master PIC mask address */
#define PIC_MASK_0          0x01      /* mask level 0                   */
#define PIC_MASK_1          0x02      /* mask level 1                   */
#define PIC_MASK_2          0x04      /* mask level 2                   */
#define PIC_MASK_3          0x08      /* mask level 3 = COM2            */
#define PIC_MASK_4          0x10      /* mask level 4 = COM1            */
#define PIC_MASK_5          0x20      /* mask level 5                   */
#define PIC_MASK_6          0x40      /* mask level 6                   */
#define PIC_MASK_7          0x80      /* mask level 7                   */



#define SIOCOM1_VECTOR  PIC_M_LEVEL + IRQ_COM1
#define SIOCOM2_VECTOR  PIC_M_LEVEL + IRQ_COM2

/* uart "physical" port addresses */
#define COM1_BASE               0x03F8
#define COM2_BASE               0x02F8
#define COM3_BASE               0x03E8
#define COM4_BASE               0x02E8
 
/* 8259 PIC addresses for End Of Interrupts */
#define PIC_M_STATUS      0x20      /* master PIC status address */
#define PIC_NSEOI         0x20      /* EOI to the specified level */
 
/* uart Line control register bits */
#define B_BREAK                 0x40    /* set break                    */
#define B_DLAB                  0x80    /* divisor latch access bit     */
 
/* uart Line status register bits */
#define B_DATA_RDY              0x01    /* receive data ready */
#define B_OVERRUN               0x02    /* overrun error */
#define B_PARITY                0x04    /* parity error */
#define B_FRAMING               0x08    /* framing error */
#define B_BREAKINT              0x10    /* break */
#define B_ERRORS                0x1E    /* B_OVERRUN|B_PARITY|B_FRAMING|B_BREAKINT */
#define B_THRE                  0x20    /* transmitter holding reg empty */
 
/* uart Modem Control Register */
#define MCR_DTR                 0x01    /* data terminal ready */
#define MCR_RTS                 0x02    /* request to send */
#define MCR_OUT1                0x04    /* general purpose output 1 */
#define MCR_OUT2                0x08    /* general purpose output 2 */
#define MCR_LOOP                0x10    /* loopback check */
 
/* uart Interrupt Enable Register */
#define IER_DI                  0x00    /* disable interrupts */
#define IER_RDA                 0x01    /* received data ready */
#define IER_THRE                0x02    /* transmitter buffer empty */
#define IER_RLSI                0x04    /* error parity/overrun/framing or break */
#define IER_MSI                 0x08    /* state-change of RS232 input line */
 
/* uart  Interrupt Identification Register */
#define IIR_MS                  0x00    /* change of a RS232 input signal */
#define IIR_IP                  0x01    /* = 0 if interrupt pending */
#define IIR_THRE                0x02    /* transmission buffer empty */
#define IIR_RDA                 0x04    /* data received */
#define IIR_RLS                 0x06    /* serialization error or break */

/* -- Fifo control register */
#define FCR_CLEAR_RX            0x02 /* Clear the RX FIFO */
#define FCR_CLEAR_TX            0x04 /* Clear the TX FIFO */
#define FCR_CLEAR_RXTX          0x06 /* Clear the RX and TX FIFO */
#define FCR_FIFO_ENABLE         0x01    /* enable FIFOs */

 

#define SIOPC_C2STOP            0x04   /* 2 stop bits */
#define SIOPC_CPARON            0x08   /* Enable parity */
#define SIOPC_CEVENP            0x10   /* Even parity */

/*
 * Function Prototypes
 */

int siopc_set_modem_status(int , int, int);
int siopc_clear_modem_status(int, int, int);
int siopc_get_modem_status(int, int);
int siopc_first_open(int, int);
int siopc_open(int, int);
int siopc_ioctl(int, int, mblk_t *);
int siopc_tx_data(int, int,  mblk_t *);
int siopc_set_port_params(int, int, int, int, int);
int siopc_init(int);
int siopc_intr_enable(siopc_port_t *, int);
int siopc_intr_srv(struct swk_irq_req  *);
int siopc_write_complete(siopc_port_t *);
int siopc_proc_stat_chg(siopc_port_t *);
int siopc_read_complete(siopc_port_t *);
int siopc_spec_recv(siopc_port_t *);
void siopc_intr();
void siopc_recover(siopc_port_t *);
int siopc_tx_break(int, int);
int siopc_control_io(int, int, int, int);
int siopc_close(int, int);
int siopc_putc(int, int, char);
char siopc_getc(int, int);
int siopc_proc_clist(siopc_port_t *);
int siopc_spl();
int siopc_splx();
int siopc_interrupt_disable(siopc_port_t *);
void siopc_interrupt_restore(siopc_port_t *, int);

void siopc_intr_com1() ;
void siopc_intr_com2() ; 
void siopc_intr_com( siopc_port_t * ) ;