📄 monbase.s
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;-============================================================
; @(#)monbase.s 7.3 4/24/96
;
; Created: Nov 1, 1990
;
; Rev 7.3 P. Rosenfeld 4/24/96 modified to incorporate NS486
; code
; Rev 7.2 J. Jefferies 11/14/94 modified to use jmps when
; instead of calls when executing BOARD_START
; Rev 7.1 J. Jefferies 11/14/94 modified to accomodate
; 386EX eval board. Removed "C" preprocessor cmds
; Rev 7.0 J. Jefferies to be preprocessed thru a ~C~
; preprocessor before assembly to support multiple asm.s
; Rev 6.0 J. Jefferies, MRI, March 24, 1993
; converted to 32 bit flat model
; Rev 1.3 G. Boehm, MRI, May 21, 1991
; Add CFEXTHK and CFUSRCODE to config tbl
;
; Rev 1.2 J. Fuchigami, MRI, March 22, 1991
; Replaced _mo_start with mo_start
;
; New rev #1.1 J. Fuchigami, MRI, March 20, 1991
; Put under SCCS
;
;-============================================================
;
; XRAYMON Board Support Base file
;
; This file contains the COLD_BOOT entry (or start point from
; another monitor or cold-boot routine).
; It also contains the configuration table (to go in ROM or RAM),
; and the Workspace data area (RAM).
;
; The equates in boardset.inc define how the monitor will
; operate.
;
; Must be assembled with asm386
;-============================================================
;
; Segments used
;
; CODE32 Code later renamed to _TEXT
; ROM ROMable data can be renamed to DATA
; DATA Workspace and monitor stack
;
;-============================================================
; include files
;-============================================================
$include (monvisi.inc) ;XRAYMON definitions
$include (boardset.inc)
%IF(%TARGET EQ %CPUI386EX) THEN (
$include (i386ex.inc) ; Initialize the 386EX I/O registers
)FI
$include (dbg.inc) ;debugging macros as needed
;-============================================================
; Externals
;-============================================================
extrn mo_start:near ;XRAYMON start address
extrn BOARD_START:near ;Board startup code
extrn CON_INIT:near ;init for console code (hook for init)
extrn CON_TERM:near ;terminate I/O connect or reconn.
; extrn INIT_MMU:near ;initialize the MMU page tables
extrn setbphk:near ;break point hook
extrn affbphk:near ;hook to check for breakpoint hook
; check if using polled input
%IF ((%CONIO AND %POLLED) ne 0) THEN (
extrn CON_IN:near ;read input
) FI
extrn IO_INIT:near ;write output
extrn CON_OUT:near ;write output
;-============================================================
; System defines/equates
;-============================================================
pe_flag equ 1 ; for setting PE bit
galias_off equ 8 ; offset of GDT alias in GDT
ialias_off equ 10H ; offset of IDT alias in GDT
data_selc equ 20H ; 1 selector for the DATA seg
gdt_lim equ 27H ; assume that 5 entries are all that are needed in GDT
idt_lim equ 377 ; 256 entries define the full IDT
CODEMACRO opprefx ; macro to change default operand size
db 66H ; when operating in real mode
ENDM
;-============================================================
; Conditional defines
;-============================================================
%SET (MULTI_TASK , 0)
;-============================================================
; Section: Code
;-============================================================
CODE32 segment public USE32 ER
name monbase
;-============================================================
;
; Entry point
;
;-============================================================
PUBLIC COLD_PC
PUBLIC start
PUBLIC RET_BOARD_START
COLD_PC proc near
;Switch the processor into PROTECTED FLAT MODEL mode
; Formerly (flatinit.inc)
; Since this code initializes either a 386 or 376 processor into protected
; mode, the first instructions at START test for component type.
; The 386 processor at reset is in real or compatibility mode: the PE bit is
; off and the D bit for CS is not set. Instructions execute in their 16-bit
; form. The 376 processor at reset has the PE bit on as well as the D bit,
; so instructions execute in their 32-bit form. Any real mode initialization
; could be done between COLD_PC and start.
nop ; NOPs are for initializing a 386
nop ; processor
start:
cli ;clear interrupts
cld ; clear direction flag
%IF(%TARGET EQ %CPUI386EX) THEN (
$include (i3excsu.inc) ; Initialize the 386EX I/O registers
)FI
%IF (%TARGET EQ %CPUNS486) THEN (
jmp BOARD_START ; do board init NOW!
RET_BOARD_START:
)FI
%IF(%GRAPHICS EQ 1) THEN (
mov ax,%METAWINDOWS_MODE
cmp ax, 0
je noinit
cmp ax, -1
je noinit
int 10h
noinit:
) FI
%INIT_SER ;these two macros produce code only if DEBUG_COM
%OUT_CHAR('A') ; is defined as other than 0
smsw bx ; check for processor (are we in real or prot mode)
test bl,1 ; use SMSW rather than MOV for speed
jnz short pestart ;note that if the code is in ROM
; Loading the GDTR at REALSTART or PESTART depends on user hardware
; returning a READY after a write to ROM otherwise problems occur.
realstart: ; if this is a 386 processor and in 16-bit real mode
opprefx ; use operand prefix to
mov eax,offset gdt_desc ; get 32-bit address of GDT pointer
opprefx ; use operand prefix to
and eax,0ffffh ; make address relative to reset area with CS:
; Important point - must give initial jmp address
; for start with cs set so the mov here works.
lgdtw cs:[eax] ; load 24 bits of base into GDTR (1)
opprefx ; use operand prefix to
mov eax,offset idt_desc ; get 32-bit address of IDT pointer
opprefx ; use operand prefix to
and eax,0ffffh ; make address relative to reset area (hi mem/rom)
lidtw cs:[eax] ; load 24 bits of base into IDTR (1)
mov ax,bx ; copy machine status word
or al,pe_flag ; set PE bit
lmsw ax ; load machine status word
jmp short next ; flush prefetch queue
pestart: ; if is a 376 processor or is in 32-bit protected mode
mov eax,offset gdt_desc ; get 32-bit address of GDT pointer
lgdt cs:[eax] ; load 32 bits of base into GDTR (1 mnemonics)
mov eax,offset idt_desc ; get 32-bit address of IDT pointer
lidt cs:[eax] ; load 32 bits of base into IDTR
next:
xor eax,eax ; initialize data selectors
mov al,data_selc ; GDT[4] is _phantom_data_
mov ds,ax
mov ss,ax
mov es,ax
mov fs,ax
mov gs,ax
test bl,1
jnz short pejump
opprefx ; use operand prefix for 386 processor jump
pejump:
jmp far ptr protected ; first far jump causes A31-A20 to drop low
; in the 386EX eval board this flash address is
; repeated at the top of each 1 meg address
; until the CSU is init'ed
protected:
%OUT_CHARP('P') ; outputs a "P" only if DEBUG_COM is defined 1 or 2
ltr cs:tr_sel ;hard coded
;Setup stack until MOINIT
%IF(%DATAAD EQ 1) THEN (
mov esp, OFFSET STACK_START-4 ; obfuscation
mov eax, OFFSET STACK_START+8 ; location of desired IDT
) ELSE (
mov esp, STACK_START-4 ; obfuscation
mov eax, STACK_START+8 ; location of desired IDT
) FI
; in order to get around problems with memory mapping
; and stack placement at this juncture we use jmps to
%IF (%TARGET NE %CPUNS486) THEN (
jmp BOARD_START ; do board init before Mon Init
RET_BOARD_START:
)FI
xor ecx, ecx
;if mo_wsp is a part of the XDM then no need to
; put a new IDT out there as well
%IF (%DATAAD EQ 0) then ( ; if MO_WSP is not in the body of xdm
mov cx, cs:idt_desc
mov esi, cs:idt_base ; pickup the current location of the IDT
mov edi, cs:ram_idt_base ; pickup the desired location of the IDT
rep movsb ; copy IDT to place
lidt cs:ram_idt_desc
)FI
;
COLD_PC_CONTINUE: ;at this point we are PROTECTED FLAT MODEL
; stack and segment registers are set up
; Clear the flags register, IMPORTANT!
xor eax,eax ; necessary to set IOPL to 0
push eax
popfd
;
xor eax, eax ;clear 0 as first init
; set up registers required by monitor
mov eax, offset COLD_PC
call mo_start+MOINIT ; initialize Monitor (no return if ok)
; input: AX = return code printed on console
; in this case loop forever
ERR_LOOP:
; jmp ERR_LOOP
PUBLIC int_def
int_def: ;default entry for exceptions, gets reset later in core code
jmp mo_start+064h ;call mon_excp unknown exception
COLD_PC endp
CODE32 ends
;-============================================================
; Segment: ROMable Data
;-============================================================
ROM segment public USE32 RO
;-============================================================
;
; XRAYMON Configuration Table
;
;-============================================================
; the following as in original
PUBLIC mo_config
%IF (%MULTI_TASK NE 0) THEN (
extrn XDM_ExtCHook:near
) FI
mo_config:
dd MO_WSP ; pointer to workspace
dd MO_WSP_SIZE ; workspace size (bytes) MO_WSP_SIZE + IDT et al
dd 0 ; pointer to codespace if 0 uses MO_WSP is used
dd 0 ; codespace size taken from flash utility
dw INIT_FLAG ; options
%IF ((%TARGET AND %CPU80386) ne 0) THEN (
dw CCPU386
) FI
%IF ((%TARGET AND %CPU80486) ne 0) THEN (
dw CCPU486
) FI
%IF ((%TARGET AND %CPUPENTIUM) ne 0) THEN (
dw CCPUPENTIUM
) FI
%IF ((%TARGET AND %CPUI386EX) ne 0) THEN (
dw CCPUI386EX
) FI
%IF ((%TARGET AND %CPUNS486) ne 0) THEN (
dw CCPUNS486
) FI
dw 0 ; delay loops before timeout
dw 0 ; max number of breakpoints
dd 0 ; breakpoint instruction
dd 0 ; breakpoint vector
dd 0 ; auxiliary monitor invoke vector
db %INTLEVEL ; interrupt level
db 0 ; reserved must be zero
dd 0 ; message buffer size
dd 0 ; input buffer size
dw CON_SCHEME ; max encoding scheme
dd %ABVECT ; abort vector
dd CON_OUT ; output poll routine
%IF ((%CONIO AND %POLLED) ne 0) THEN (
dd CON_IN ; polled input
) ELSE (
dd 0 ; else interrupt input
) FI
dd setbphk ; set breakpoint hook
dd affbphk ; affect breakpoint hook
dd CON_INIT ; initialization hook
dd 0 ; idle hook
dd 0 ; interrupt enable/disable hook
dd CON_TERM ; auxiliary monitor hook
dd 0 ; start/stop execution hook
dd 0 ; human component pointer
%IF (%MULTI_TASK NE 0) THEN (
dd XDM_ExtCHook ; extension hook
) ELSE (
dd 0 ; extension hook
) FI
dd %BASEAD ; start of xdm code area (for protect)
; have include GDT IDT and 72H of buffer
dd 0 ; reserved
dd 0 ; reserved
dd 0 ; CFAUTOSTHK
;
; MRI/1 version of GDT IDT descriptors
PUBLIC gdt_desc, gdt_base
PUBLIC idt_desc, idt_base
PUBLIC tr_sel
;
tr_sel dw 030H
;
gdt_desc dw ? ;this is set by builder as 6 bytes of descriptor
gdt_base dd ? ; pointing at GDT within body of XDM (possibly ROM)
;
idt_desc dw ? ;this is set by builder as 6 bytes of descriptor
idt_base dd ? ; pointing at IDT within body of XDM (possibly ROM)
;
%IF (%DATAAD EQ 0) then (
PUBLIC ram_idt_desc, ram_idt_base
ram_idt_desc dw 07ffH ; this is the hand built version of the idt_desc pointing
ram_idt_base dd INTERRUPT_DESC_TBL ; at where we want it in RAM along with MO_WSP
ROM ends
)ELSE(
ROM ends
;-============================================================
; Section: Normal Data
;-============================================================
;
; XRAYMON Workspace
;
DATA segment public USE32 RW
PUBLIC MO_WSP
PUBLIC STACK_START
MO_WSP:
db MO_WSP_SIZE dup (?)
STACK_START:
dd ? ;just for safety
dd ? ;just for safety
DATA ends
)FI
END
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