n8250.ieq

VRTX 商用嵌入式实时操作系统

; ====================================================================
;	@(#)n8250.ieq	5.1	5/7/91
;
; N8250.IEQ - I/O equates for 8250 UART
;   NS16C450 and INS8250A
;
; Module Name:	n8250.ieq
; Module Desc:	include file (as hwequ.inc) for board.src 
; Created:	Nov. 1990
;
;	New rev #1.1	J. Fuchigami, MRI, March 20, 1991
;			Put under SCCS
;
; Revision:	1.0
; --------------------------------------------------------------------
; General Information:
;
; ====================================================================
;---------------------------------------------------------------------
; UART addresses - Device is National 8250 UART
;---------------------------------------------------------------------
DATA_REG EQU %IOBASE	               ;send/rec buffer
STATUS_REG EQU %IOBASE+%IOOFF*5      ;status register
;---------------------------------------------------------------------
; Status Register bits
RBFULL		equ	1		;receive buffer full mask
OVERRUN_ERR	equ	2		;overrun error
PARITY_ERR	equ	4		;parity error
FRAME_ERR	equ	08h		;framing error
TBEMPTY		equ	20H		;transmit buffer empty mask
; Baud Rate registers
BAL_REG EQU %IOBASE		;baud rate low
BAH_REG EQU %IOBASE+%IOOFF	;baud rate high
; Interrupt Enable Register
IER_REG EQU %IOBASE+%IOOFF
IER_REC_INT	equ	1		;receive interrupt
IER_XMIT_INT	equ	2		;transmit interrupt
; Line Configure Register
LCR_REG EQU %IOBASE+%IOOFF*3
LCR_DLAB	equ	80h		;select divisor latch
%IF (%PARITY EQ %PAR_NONE) THEN (
LCR_LENGTH	equ	3		;8 bits
) ELSE ( 
LCR_LENGTH	equ	2		;7 bits
) FI
%IF (%PARITY EQ %PAR_NONE) THEN (
LCR_PARITY	equ	0		;no parity
) FI
%IF (%PARITY EQ %PAR_ODD) THEN (
LCR_PARITY	equ	8		;odd parity
) FI
%IF (%PARITY EQ %PAR_EVEN) THEN (
LCR_PARITY	equ	18h		;even parity
) FI
%IF (%PARITY EQ %PAR_SPACE) THEN (
LCR_PARITY	equ	38h		;low parity
) FI
%IF (%PARITY EQ %PAR_MARK) THEN (
LCR_PARITY	equ	28h		;high parity
) FI
; the following are the baud rate constants based
; on a 16x divisor and a clock of 1.843 MHz
%IF (%BAUD EQ 0) THEN (
BAUD_COUNT EQU 0
) FI
%IF (%BAUD EQ %IO115200) THEN ( 
BAUD_COUNT EQU 1		;115200 baud
) FI
%IF (%BAUD EQ %IO57600) THEN ( 
BAUD_COUNT EQU 2		;57600 baud
) FI
%IF (%BAUD EQ %IO38400) THEN (
BAUD_COUNT EQU 3		;38400 baud
) FI
%IF (%BAUD EQ %IO19200) THEN (
BAUD_COUNT EQU 6		;19200 baud
) FI
%IF (%BAUD EQ %IO9600) THEN (
BAUD_COUNT EQU 12		;9600 baud
) FI
%IF (%BAUD EQ %IO4800) THEN (
BAUD_COUNT EQU 24		;4800 baud
) FI
%IF (%BAUD EQ %IO2400) THEN (
BAUD_COUNT EQU 48		;2400 baud
) FI
%IF (%BAUD EQ %IO1200) THEN (
BAUD_COUNT EQU 96		;1200 baud
) FI

; 8259 INTERRUPT CONTROLLER
%SET (NUM_8259, 2)              ;set the number of 8259's 1 or 2

MASTER_8259 EQU 020H		;I/O space address of 8259
SLAVE_8259  EQU 0A0H
%IF (%IOINTVECT eq 0) THEN(
MASTER_8259_BASE EQU 038H           ;base for interrupts from the 1st 8259
SLAVE_8259_BASE  EQU 040H           ;base of interrupts for the 2nd 8259 lwr 3 bits
                                     ;must be 0
)ELSE(
MASTER_8259_BASE EQU %IOINTVECT ;base for interrupts from the 1st 8259
SLAVE_8259_BASE  EQU MASTER_8259_BASE + 8  ;base of interrupts for the 2nd 8259 
)FI
COM1_INTERRUPT EQU MASTER_8259_BASE + 4 ;this is normally vector 60
COM2_INTERRUPT EQU MASTER_8259_BASE + 3 ;this is normally vector 59

                                           ;lwr 3 bits must be 0