ns486reg.inc

VRTX 商用嵌入式实时操作系统

DMA_BRA2      equ 00012h  ; r/w  16  Base Requestor Address 2
DMA_BRA3      equ 00016h  ; r/w  16  Base Requestor Address 3
DMA_BRA4      equ 00014h  ; r/w  16  Base Requestor Address 4

                               ;          (r current, w base)
                               ;          (Note: 10 bit Registers)
DMA_BRAP0     equ 00088h  ; r/w  16  Base/Curr. Requestor Address Pg. 0
DMA_BRAP2     equ 0008Ah  ; r/w  16  Base/Curr. Requestor Address Pg. 2
DMA_BRAP3     equ 0008Eh  ; r/w  16  Base/Curr. Requestor Address Pg. 3
DMA_BRAP4     equ 0008Ch  ; r/w  16  Base/Curr. Requestor Address Pg. 4

                               ;          (r current, w base)
DMA_BBC0      equ 000CCh  ; r/w  16  Base/Current Byte Count 0
DMA_BBC1      equ 000CEh  ; r/w  16  Base/Current Byte Count 1
DMA_BBC2      equ 000D0h  ; r/w  16  Base/Current Byte Count 2
DMA_BBC3      equ 000D2h  ; r/w  16  Base/Current Byte Count 3
DMA_BBC4      equ 000D4h  ; r/w  16  Base/Current Byte Count 4
DMA_BBC5      equ 000D6h  ; r/w  16  Base/Current Byte Count 5

;---------------------------------------------------------------------------

; DRAM Controller
;   entered mcd - 1995.07.27

DRAM_CONTROL  equ 0EF80h  ; r/w  16  DRAM Control Register
DRAM_REFRESH  equ 0EF82h  ; r/w  16  Refresh Rate Register
DRAM_RAS      equ 0EF84h  ; r/w  16  RAS* Timeout Register
DRAM_STATUS   equ 0EF86h  ; r/w  16  DRAM Status Register
DRAM_BANK     equ 0EF88h  ; r/w   8  DRAM Bank Size Register
DRAM_ADDR1    equ 0EF89h  ; r/w   8  Bank 1 Address Register
DRAM_MASK0    equ 0EF8Ah  ; r/w   8  Bank 0 Mask Register
DRAM_MASK1    equ 0EF8Bh  ; r/w   8  Bank 1 Mask Register

;---------------------------------------------------------------------------

; ECP Port - IEEE 1284 Bidirectional Parallel Port
;   entered mcd - 1995.07.27
;   enclosed with IFDEF - 1995.09.28


; ECP_BASE needs to be defined as one of the following in the file
; including this one.  This is because several possible bases are
; allowed, but only one is configured for use.

ECP_BASE1     equ 00278h  ; */*  **  ECP option 1 register base
ECP_BASE2     equ 00378h  ; */*  **  ECP option 2 register base
ECP_BASE3     equ 003BCh  ; */*  **  ECP option 3 register base

ECP_BASE	  equ ECP_BASE1
;

ECP_DATAR     equ ECP_BASE + 0000h  ; r/w   8  DATAR Register
ECP_AFIFO     equ ECP_BASE + 0000h  ;  /w   8  AFIFO Register
ECP_DSR       equ ECP_BASE + 0001h  ; r/    8  DSR Register
ECP_DCR       equ ECP_BASE + 0002h  ; r/w   8  DCR Register
ECP_CFIFO     equ ECP_BASE + 0400h  ; r/w   8  CFIFO Register
ECP_DFIFO     equ ECP_BASE + 0400h  ;  /w   8  DFIFO Register
ECP_TFIFO     equ ECP_BASE + 0400h  ; r/w   8  TFIFO Register
ECP_CNFGA     equ ECP_BASE + 0400h  ; r/w   8  ECP CONFIG_A Register
ECP_CNFGB     equ ECP_BASE + 0401h  ; r/w   8  ECP CONFIG_B Register
ECP_ECR       equ ECP_BASE + 0402h  ; r/w   8  ECR Register
ECP_IPR       equ ECP_BASE + 0405h  ; r/w   8  IPR Register

ECP_INDEX     equ ECP_BASE + 0403h  ; r/w   8  ECP INDEX Register
ECP_SETUP     equ ECP_BASE + 0404h  ; r/w   8  ECP SETUP Register

;


;---------------------------------------------------------------------------

; LCD Controller
;   entered mcd - 1995.07.27

LCD_CFG1      equ 0EFA0h  ; r/w   8  LCD Configuration Reg. 1
LCD_CFG2      equ 0EFA1h  ; r/w   8  LCD Configuration Reg. 2
LCD_CFG3      equ 0EFA2h  ; r/w   8  LCD Configuration Reg. 3
LCD_CFG4      equ 0EFA3h  ; r/w   8  LCD Configuration Reg. 4

;---------------------------------------------------------------------------

; PCMCIA Controller
;   entered mcd - 1995.07.27
;   alternate base address added mcd - 1995.08.07
;   enclosed with IFDEF - 1995.09.28


; PCM_BASE needs to be defined as one of the following in the file
; including this one.  This is because several possible bases are
; allowed, but only one is configured for use.

PCM_BASE1     equ 003E0h  ; */*  **  PCMCIA option 1 register base
PCM_BASE2     equ 003E2h  ; */*  **  PCMCIA option 2 register base

PCM_BASE equ PCM_BASE1

PCM_INDEX     equ PCM_BASE + 00h    ; r/w   8  PCMCIA Index
PCM_DATA      equ PCM_BASE + 01h    ; r/w   8  PCMCIA Data

;


;---------------------------------------------------------------------------

; Programmable Interrupt Controller (PIC)
;   entered mcd - 1995.07.27

PIC_MASTER0   equ 00020h  ; r/w   8  Master PIC port 0
PIC_MASTER1   equ 00021h  ; r/w   8  Master PIC port 1
PIC_SLAVE0    equ 000A0h  ; r/w   8  Slave PIC port 0
PIC_SLAVE1    equ 000A1h  ; r/w   8  Slave PIC port 1

PIC_M_ICW1    equ PIC_MASTER0        ; r/w   8  Master ICW1
PIC_M_ICW2    equ PIC_MASTER1        ; r/w   8  Master ICW2
PIC_M_ICW3    equ PIC_MASTER1        ; r/w   8  Master ICW3
PIC_M_ICW4    equ PIC_MASTER1        ; r/w   8  Master ICW4
PIC_M_OCW1    equ PIC_MASTER1        ; r/w   8  Master OCW1
PIC_M_OCW2    equ PIC_MASTER0        ; r/w   8  Master OCW2
PIC_M_OCW3    equ PIC_MASTER0        ; r/w   8  Master OCW3

PIC_S_ICW1    equ PIC_SLAVE0         ; r/w   8  Slave ICW1
PIC_S_ICW2    equ PIC_SLAVE1         ; r/w   8  Slave ICW2
PIC_S_ICW3    equ PIC_SLAVE1         ; r/w   8  Slave ICW3
PIC_S_ICW4    equ PIC_SLAVE1         ; r/w   8  Slave ICW4
PIC_S_OCW1    equ PIC_SLAVE1         ; r/w   8  Slave OCW1
PIC_S_OCW2    equ PIC_SLAVE0         ; r/w   8  Slave OCW2
PIC_S_OCW3    equ PIC_SLAVE0         ; r/w   8  Slave OCW3

PIC_M_IRR     equ PIC_M_OCW3         ; r/w   8  Master IRR
PIC_M_IMR     equ PIC_M_OCW1         ; r/w   8  Master IMR
PIC_M_ISR     equ PIC_M_OCW3         ; r/w   8  Master ISR

PIC_S_IRR     equ PIC_S_OCW3         ; r/w   8  Slave IRR
PIC_S_IMR     equ PIC_S_OCW1         ; r/w   8  Slave IMR
PIC_S_ISR     equ PIC_S_OCW3         ; r/w   8  Slave ISR

PIC_II1SR     equ 0EFB1h  ; r/w   8  Internal Interrupt  1 Sel. Reg.
PIC_II3SR     equ 0EFB3h  ; r/w   8  Internal Interrupt  3 Sel. Reg.
PIC_II4SR     equ 0EFB4h  ; r/w   8  Internal Interrupt  4 Sel. Reg.
PIC_II5SR     equ 0EFB5h  ; r/w   8  Internal Interrupt  5 Sel. Reg.
PIC_II6SR     equ 0EFB6h  ; r/w   8  Internal Interrupt  6 Sel. Reg.
PIC_II7SR     equ 0EFB7h  ; r/w   8  Internal Interrupt  7 Sel. Reg.
PIC_II9SR     equ 0EFB9h  ; r/w   8  Internal Interrupt  9 Sel. Reg.
PIC_II10SR    equ 0EFBAh  ; r/w   8  Internal Interrupt 10 Sel. Reg.
PIC_II11SR    equ 0EFBBh  ; r/w   8  Internal Interrupt 11 Sel. Reg.
PIC_II12SR    equ 0EFBCh  ; r/w   8  Internal Interrupt 12 Sel. Reg.
PIC_II13SR    equ 0EFBDh  ; r/w   8  Internal Interrupt 13 Sel. Reg.
PIC_II14SR    equ 0EFBEh  ; r/w   8  Internal Interrupt 14 Sel. Reg.
PIC_II15SR    equ 0EFBFh  ; r/w   8  Internal Interrupt 15 Sel. Reg.

;---------------------------------------------------------------------------

; Programmable Interval Timer (PIT)
;   entered mcd - 1995.07.27

PIT_COUNT0    equ 00040h  ; r/w   8  Counter 0
PIT_COUNT1    equ 00041h  ; r/w   8  Counter 1
PIT_COUNT2    equ 00042h  ; r/w   8  Counter 2
PIT_CONTROL   equ 00043h  ;  /w   8  Timer Control Register
PIT_TICR      equ 00044h  ; r/w   8  Timer I/O Control Register
PIT_CLOCK     equ 00045h  ; r/w   8  Timer Clock Register

;---------------------------------------------------------------------------

; Power Management
;   entered mcd - 1995.07.27

PM_PMR1       equ 0EF90h  ; r/w   8  Power Management Register 1
PM_PMR2       equ 0EF91h  ; r/w   8  Power Management Register 2
PM_PMR3       equ 0EF92h  ; r/w   8  Power Management Register 3
PM_PMR4       equ 0EF93h  ; r/w   8  Power Management Register 4

;---------------------------------------------------------------------------

; Reconfigurable I/O
;   entered mcd - 1995.07.27

RIO_CONTROL   equ 0EFC0h  ; r/w   8  RIO Control Register

RIO_DD        equ 0EFC4h  ; r/w  32  Data Direction Register
RIO_DD_WORD0  equ 0EFC4h  ; r/w  16  Data Direction Word 0
RIO_DD_BYTE0  equ 0EFC4h  ; r/w   8  Data Direction Byte 0
RIO_DD_BYTE1  equ 0EFC5h  ; r/w   8  Data Direction Byte 1
RIO_DD_WORD1  equ 0EFC6h  ; r/w  16  Data Direction Word 1
RIO_DD_BYTE2  equ 0EFC6h  ; r/w   8  Data Direction Byte 2
RIO_DD_BYTE3  equ 0EFC7h  ; r/w   8  Data Direction Byte 3

RIO_DI        equ 0EFC8h  ; r/w  32  Data Port In Register
RIO_DI_WORD0  equ 0EFC8h  ; r/w  16  Data Input Word 0
RIO_DI_BYTE0  equ 0EFC8h  ; r/w   8  Data Input Byte 0
RIO_DI_BYTE1  equ 0EFC9h  ; r/w   8  Data Input Byte 1
RIO_DI_WORD1  equ 0EFCAh  ; r/w  16  Data Input Word 1
RIO_DI_BYTE2  equ 0EFCAh  ; r/w   8  Data Input Byte 2
RIO_DI_BYTE3  equ 0EFCBh  ; r/w   8  Data Input Byte 3

RIO_DO        equ 0EFCCh  ; r/w  32  Data Port Out Register
RIO_DO_WORD0  equ 0EFCCh  ; r/w  16  Data Output Word 0
RIO_DO_BYTE0  equ 0EFCCh  ; r/w   8  Data Output Byte 0
RIO_DO_BYTE1  equ 0EFCDh  ; r/w   8  Data Output Byte 1
RIO_DO_WORD1  equ 0EFCEh  ; r/w  16  Data Output Word 1
RIO_DO_BYTE2  equ 0EFCEh  ; r/w   8  Data Output Byte 2
RIO_DO_BYTE3  equ 0EFCFh  ; r/w   8  Data Output Byte 3

;---------------------------------------------------------------------------

; Real Time Clock

RTC_INDEX     equ 00070h  ; r/w   8  RTC Index
RTC_DATA      equ 00071h  ; r/w   8  RTC Data

;---------------------------------------------------------------------------

; Three Wire Interface
;   entered mcd - 1995.07.27
;   added TWI_A_CTRL2 and TWI_U_SCS - 1995.11.16

TWI_CONTROL   equ 00050h  ; r/w   8  3-Wire Control Register
TWI_SIO       equ 00051h  ; r/w   8  3-Wire Serial I/O Register
TWI_U_CONTROL equ 00052h  ; r/w   8  Microwire Control Register
TWI_SDA       equ 00053h  ; r/w   8  Serial Input/Output Data Register
TWI_A_STATUS  equ 00054h  ; r/    8  Access.bus Status Register
TWI_A_CONTROL equ 00055h  ; r/w   8  Access.bus Control Register
TWI_A_ADDR    equ 00056h  ; r/w   8  Access.bus Own Address Register
TWI_A_CTRL2   equ 00057h  ; r/w   8  Access.bus Control Register 2
TWI_U_SCS     equ 0EFC1h  ; r/w   8  Microwire Slave Chip Select Reg.

;---------------------------------------------------------------------------

; UART
;   entered mcd - 1995.07.27
;   enclosed with IFDEF - 1995.09.28


; UART_BASE needs to be defined as one of the following in the file
; including this one.  This is because several possible bases are
; allowed, but only one is configured for use.

UART_COM1     equ 003F8h  ; */*  **  UART COM 1 register base
UART_COM2     equ 002F8h  ; */*  **  UART COM 2 register base
UART_COM3     equ 003E8h  ; */*  **  UART COM 3 register base
UART_COM4     equ 002E8h  ; */*  **  UART COM 3 register base

UART_BASE equ UART_COM2

UART_CLOCK    equ 0EF70h  ; r/w   8  UART Clock Divisor Register
UART_MSC      equ 0EF71h  ; r/w   8  Modem Signal Control Register

UART_RBR      equ UART_BASE + 00h  ; r/    8  Receiver Buffer Reg.
UART_THR      equ UART_BASE + 00h  ;  /w   8  Transmit Holding Reg.
UART_IER      equ UART_BASE + 01h  ; r/w   8  Interrupt Enable Reg.
UART_IIR      equ UART_BASE + 02h  ; r/    8  Interrupt Id. Reg.
UART_FCR      equ UART_BASE + 02h  ;  /w   8  FIFO Control Reg.
UART_LCR      equ UART_BASE + 03h  ; r/w   8  Line Control Reg.
UART_MCR      equ UART_BASE + 04h  ; r/w   8  Modem Control Reg.
UART_LSR      equ UART_BASE + 05h  ; r/w   8  Line Status Reg.
UART_MSR      equ UART_BASE + 06h  ; r/w   8  Modem Status Reg.
UART_SCR      equ UART_BASE + 07h  ; r/w   8  Scratch Pad Reg.
UART_DLL      equ UART_BASE + 00h  ; r/w   8  Divisor Latch LSB
UART_DLM      equ UART_BASE + 01h  ; r/w   8  Divisor Latch MSB

;


;---------------------------------------------------------------------------

; Watchdog Timer
;   entered mcd - 1995.07.27

WD_RETRIGGER  equ 00046h  ; r/w  16  Watchdog Retrigger
WD_CONTROL    equ 00047h  ; r/w   8  Watchdog Control Register

;---------------------------------------------------------------------------


;---------------------------------------------------------------------------
; END       ns486reg.inc
;---------------------------------------------------------------------------