ns486reg.inc

VRTX 商用嵌入式实时操作系统

;---------------------------------------------------------------------------
;
; FILE     ns486reg.inc
; TYPE     Assembly header
; VERSION  1.9
; LONGVER  GEN1.9
; CLASS    beta
; STATUS   complete
; CREATED  1995.07.27
; REVISED  1996.02.06
; AUTHOR   Michael C. Draeger
; PROJECT  NS486SXF General
; PART     NS486SXF B0
; SUMMARY  NS486SXF Register locations
; RCS      $Id: ns486reg.inc,v 1.2 1996/02/07 01:16:30 miked Exp $
;
; DESCRIPTION
;
;   This header file contains the locations of every register in the
;   NS486SXF.  It should be used in Assembly language programs to
;   access registers symbolically.
;
;   For each register the file indicates (in the comment) the name of
;   the register, when it is readable, whether it is writeable, and the
;   width (8, 16, 32) of the register.
;
; NAMING CONVENTION
;
;   block_regname
;
;       block = block in NS486SXF
;       regname = Register abbreviation / name
;
;     blocks
;
;       BIU     Bus Interface Unit
;       DMA     DMA Controller
;       DRAM    DRAM Controller
;       ECP     ECP Port (IEEE 1284 Bidirectional Parallel Port)
;       LCD     LCD Controller
;       NS486   NS486 device ID registers
;       PCM     PCMCIA
;       PIC     Programmable Interrupt Controller
;       PIT     Programmable Interval Timer
;       PM      Power Management
;       RIO     Reconfigurable I/O
;       RTC     Real Time Clock
;       TWI     Three Wire Interface
;       UART    UART
;       WD      Watchdog Timer
;
; INPUTS
;
;   ECP_BASE -  can be defined as ECP_BASE1, ECP_BASE2, or ECP_BASE3
;               before including this header to indicate where the
;               ECP port is mapped in the part.  The three possible
;               values are:
;
;                 ECP_BASE1     0x00278
;                 ECP_BASE2     0x00378
;                 ECP_BASE3     0x003BC
;
;   PCM_BASE -  can be defined as PCM_BASE1 or PCM_BASE2 before including
;               this header to indicate where the PCMCIA controller is
;               mapped in the part.  The possible values are:
;
;                 PCM_BASE1     0x003E0
;                 PCM_BASE2     0x003E2
;
;   UART_BASE - can be defined as UART_COM1, UART_COM2, UART_COM3, or
;               UART_COM4 before including this header to indicate where
;               the UART is mapped in the part.  The possible values are:
;
;                 UART_COM1     0x003F8
;                 UART_COM2     0x002F8
;                 UART_COM3     0x003E8
;                 UART_COM4     0x002E8
;
; HISTORY/CONTRIBUTORS
;
;   1.0   1995.07.27  mcd  genesis
;   1.1   1995.07.31  mcd  fixed missing comments delimiters
;   1.2   1995.08.07  mcd  added alternate PCMCIA register locations
;                          and cleaned up some register names to make
;                          them more unique
;   1.3   1995.08.22  mcd  renamed misc registers
;   1.4   1995.09.28  mcd  modifed for MAW
;   1.5   1995.11.16  mcd  added two registers for the three wire interface
;   1.6   1995.12.01  mcd  updated DMA for rev B part
;   1.7   1996.01.31  mcd  removed E_ convention, added NS486_ for ID regs,
;                          removed designer notes, fixed DMA address and
;                          byte count registers for rev B
;   1.8   1996.02.06  mcd  cosmetic changes, based off "ns486"
;   1.9   1996.02.06  mcd  added comments to INPUTS section above
;
;   (mcd = Michael C. Draeger)
;
; COPYRIGHT
;
;      (c) 1995, 1996 National Semiconductor Corporation
;
; NOTES
;
;---------------------------------------------------------------------------

NS486REG_INC_INC equ 1

;---------------------------------------------------------------------------

;NS486REG_INC_VERSION equ "1.9"
;NS486REG_INC_DATE    equ "1996.02.06"

;---------------------------------------------------------------------------

; NS486SXF ID registers
;   entered mcd - 1995.08.22
;   NS486_ added mcd - 1996.01.31

NS486_ID      equ 0EFC2h  ; r/    8  NS486SXF Device ID Register
NS486_REV     equ 0EFC3h  ; r/    8  NS486SXF Revision Number

;---------------------------------------------------------------------------

; Bus Interface Unit
;   entered mcd - 1995.07.27

BIU_CONTROL1  equ 0EF00h  ; r/w   8  BIU Control Register 1
BIU_CONTROL2  equ 0EF01h  ; r/w   8  BIU Control Register 2
BIU_CS_EN     equ 0EF02h  ; r/w   8  Chip Select Enable
BIU_CS_TYPE   equ 0EF03h  ; r/w   8  Chip Select Type

                               ; note: you can access as 16 bit registers
                               ; (even addresses)
BIU_CSBAR1_0  equ 0EF04h  ; r/w   8  CS Base Address Reg 1 byte 0
BIU_CSBAR1_1  equ 0EF05h  ; r/w   8  CS Base Address Reg 1 byte 1
BIU_CSBAR1_2  equ 0EF06h  ; r/w   8  CS Base Address Reg 1 byte 2
BIU_CSBAR1_3  equ 0EF07h  ; r/w   8  CS Base Address Reg 1 byte 3
BIU_CSBAR2_0  equ 0EF08h  ; r/w   8  CS Base Address Reg 2 byte 0
BIU_CSBAR2_1  equ 0EF09h  ; r/w   8  CS Base Address Reg 2 byte 1
BIU_CSBAR2_2  equ 0EF0Ah  ; r/w   8  CS Base Address Reg 2 byte 2
BIU_CSBAR2_3  equ 0EF0Bh  ; r/w   8  CS Base Address Reg 2 byte 3
BIU_CSBAR3_0  equ 0EF0Ch  ; r/w   8  CS Base Address Reg 3 byte 0
BIU_CSBAR3_1  equ 0EF0Dh  ; r/w   8  CS Base Address Reg 3 byte 1
BIU_CSBAR3_2  equ 0EF0Eh  ; r/w   8  CS Base Address Reg 3 byte 2
BIU_CSBAR3_3  equ 0EF0Fh  ; r/w   8  CS Base Address Reg 3 byte 3
BIU_CSBAR4_0  equ 0EF10h  ; r/w   8  CS Base Address Reg 4 byte 0
BIU_CSBAR4_1  equ 0EF11h  ; r/w   8  CS Base Address Reg 4 byte 1
BIU_CSBAR4_2  equ 0EF12h  ; r/w   8  CS Base Address Reg 4 byte 2
BIU_CSBAR4_3  equ 0EF13h  ; r/w   8  CS Base Address Reg 4 byte 3
BIU_CSBAR5_0  equ 0EF14h  ; r/w   8  CS Base Address Reg 5 byte 0
BIU_CSBAR5_1  equ 0EF15h  ; r/w   8  CS Base Address Reg 5 byte 1
BIU_CSBAR5_2  equ 0EF16h  ; r/w   8  CS Base Address Reg 5 byte 2
BIU_CSBAR5_3  equ 0EF17h  ; r/w   8  CS Base Address Reg 5 byte 3
BIU_CSBAR6_0  equ 0EF18h  ; r/w   8  CS Base Address Reg 6 byte 0
BIU_CSBAR6_1  equ 0EF19h  ; r/w   8  CS Base Address Reg 6 byte 1
BIU_CSBAR6_2  equ 0EF1Ah  ; r/w   8  CS Base Address Reg 6 byte 2
BIU_CSBAR6_3  equ 0EF1Bh  ; r/w   8  CS Base Address Reg 6 byte 3
BIU_CSBAR7_0  equ 0EF1Ch  ; r/w   8  CS Base Address Reg 7 byte 0
BIU_CSBAR7_1  equ 0EF1Dh  ; r/w   8  CS Base Address Reg 7 byte 1
BIU_CSBAR7_2  equ 0EF1Eh  ; r/w   8  CS Base Address Reg 7 byte 2
BIU_CSBAR7_3  equ 0EF1Fh  ; r/w   8  CS Base Address Reg 7 byte 3
BIU_CSBAR8_0  equ 0EF20h  ; r/w   8  CS Base Address Reg 8 byte 0
BIU_CSBAR8_1  equ 0EF21h  ; r/w   8  CS Base Address Reg 8 byte 1
BIU_CSBAR8_2  equ 0EF22h  ; r/w   8  CS Base Address Reg 8 byte 2
BIU_CSBAR8_3  equ 0EF23h  ; r/w   8  CS Base Address Reg 8 byte 3

                               ; note: you can access as 16 bit registers
                               ; (even addresses)
BIU_CSARR1_0  equ 0EF24h  ; r/w   8  CS Address Range Reg 1 byte 0
BIU_CSARR1_1  equ 0EF25h  ; r/w   8  CS Address Range Reg 1 byte 1
BIU_CSARR1_2  equ 0EF26h  ; r/w   8  CS Address Range Reg 1 byte 2
BIU_CSARR1_3  equ 0EF27h  ; r/w   8  CS Address Range Reg 1 byte 3
BIU_CSARR2_0  equ 0EF28h  ; r/w   8  CS Address Range Reg 2 byte 0
BIU_CSARR2_1  equ 0EF29h  ; r/w   8  CS Address Range Reg 2 byte 1
BIU_CSARR2_2  equ 0EF2Ah  ; r/w   8  CS Address Range Reg 2 byte 2
BIU_CSARR2_3  equ 0EF2Bh  ; r/w   8  CS Address Range Reg 2 byte 3
BIU_CSARR3_0  equ 0EF2Ch  ; r/w   8  CS Address Range Reg 3 byte 0
BIU_CSARR3_1  equ 0EF2Dh  ; r/w   8  CS Address Range Reg 3 byte 1
BIU_CSARR3_2  equ 0EF2Eh  ; r/w   8  CS Address Range Reg 3 byte 2
BIU_CSARR3_3  equ 0EF2Fh  ; r/w   8  CS Address Range Reg 3 byte 3
BIU_CSARR4_0  equ 0EF30h  ; r/w   8  CS Address Range Reg 4 byte 0
BIU_CSARR4_1  equ 0EF31h  ; r/w   8  CS Address Range Reg 4 byte 1
BIU_CSARR4_2  equ 0EF32h  ; r/w   8  CS Address Range Reg 4 byte 2
BIU_CSARR4_3  equ 0EF33h  ; r/w   8  CS Address Range Reg 4 byte 3
BIU_CSARR5_0  equ 0EF34h  ; r/w   8  CS Address Range Reg 5 byte 0
BIU_CSARR5_1  equ 0EF35h  ; r/w   8  CS Address Range Reg 5 byte 1
BIU_CSARR5_2  equ 0EF36h  ; r/w   8  CS Address Range Reg 5 byte 2
BIU_CSARR5_3  equ 0EF37h  ; r/w   8  CS Address Range Reg 5 byte 3
BIU_CSARR6_0  equ 0EF38h  ; r/w   8  CS Address Range Reg 6 byte 0
BIU_CSARR6_1  equ 0EF39h  ; r/w   8  CS Address Range Reg 6 byte 1
BIU_CSARR6_2  equ 0EF3Ah  ; r/w   8  CS Address Range Reg 6 byte 2
BIU_CSARR6_3  equ 0EF3Bh  ; r/w   8  CS Address Range Reg 6 byte 3
BIU_CSARR7_0  equ 0EF3Ch  ; r/w   8  CS Address Range Reg 7 byte 0
BIU_CSARR7_1  equ 0EF3Dh  ; r/w   8  CS Address Range Reg 7 byte 1
BIU_CSARR7_2  equ 0EF3Eh  ; r/w   8  CS Address Range Reg 7 byte 2
BIU_CSARR7_3  equ 0EF3Fh  ; r/w   8  CS Address Range Reg 7 byte 3
BIU_CSARR8_0  equ 0EF40h  ; r/w   8  CS Address Range Reg 8 byte 0
BIU_CSARR8_1  equ 0EF41h  ; r/w   8  CS Address Range Reg 8 byte 1
BIU_CSARR8_2  equ 0EF42h  ; r/w   8  CS Address Range Reg 8 byte 2
BIU_CSARR8_3  equ 0EF43h  ; r/w   8  CS Address Range Reg 8 byte 3

BIU_RBSR      equ 0EF44h  ; r/w   8  ROM BIOS Selection Register
BIU_ECSSR1    equ 0EF45h  ; r/w   8  External CS Selection Reg 1
BIU_ECSSR2    equ 0EF46h  ; r/w   8  External CS Selection Reg 2
BIU_ECSSR3    equ 0EF47h  ; r/w   8  External CS Selection Reg 3
BIU_ECSSR4    equ 0EF48h  ; r/w   8  External CS Selection Reg 4
BIU_ECSSR5    equ 0EF49h  ; r/w   8  External CS Selection Reg 5
BIU_ECSSR6    equ 0EF4Ah  ; r/w   8  External CS Selection Reg 6
BIU_ECSSR7    equ 0EF4Bh  ; r/w   8  External CS Selection Reg 7
BIU_ECSSR8    equ 0EF4Ch  ; r/w   8  External CS Selection Reg 8

BIU_PBMAR     equ 0EF4Eh  ; r/w   8  PCMCIA Base Memory Address Reg.
BIU_PCLOCK    equ 0EF4Fh  ; r/w   8  PCMCIA Clock Selection Register

BIU_CSATR1    equ 0EF50h  ; r/w   8  CS Access Time Register 1
BIU_CSATR2    equ 0EF51h  ; r/w   8  CS Access Time Register 2
BIU_CSATR3    equ 0EF52h  ; r/w   8  CS Access Time Register 3
BIU_CSATR4    equ 0EF53h  ; r/w   8  CS Access Time Register 4

BIU_RBATR     equ 0EF54h  ; r/w   8  ROM BIOS Access Time Register
BIU_CCSR      equ 0EF55h  ; r/w   8  Cacheable Chip Selects Register
BIU_EMCSSR    equ 0EF56h  ; r/w   8  External Master CS Sel. Reg.
BIU_P16LCSR   equ 0EF57h  ; r/w   8  Programmed 16-bit Logical CS Reg.

BIU_MIER1     equ 0EFB0h  ; r/w   8  Misc. Interrupt Enables Reg. 1
BIU_MIER2     equ 0EFB2h  ; r/w   8  Misc. Interrupt Enables Reg. 2
BIU_MIER3     equ 0EFB8h  ; r/w   8  Misc. Interrupt Enabled Reg. 3

;---------------------------------------------------------------------------

; DMA Controller
;   entered mcd - 1995.07.27
;   rev B TCS and COMMAND register change mcd - 1995.12.01
;   rev B changes in address/byte count mcd 1996.01.31

DMA_COMMAND   equ 00008h  ; r/w   8  DMA Command Register
DMA_RQS       equ 00009h  ; r/    8  Request Status Register
DMA_DMR0      equ 00009h  ;  /w   8  Data Mode Register CH0-CH3
DMA_TCS       equ 0000Ah  ; r/w   8  TC Status Register
DMA_CMR0      equ 0000Bh  ;  /w   8  Channel Mode Register CH0-CH3
DMA_CLEAR     equ 0000Dh  ;  /w   8  Master Clear
DMA_CMASK     equ 0000Eh  ;  /w   8  Clear Mask
DMA_MASK      equ 0000Fh  ; r/w   8  Mask Register
DMA_CHAIN0    equ 000DAh  ;  /w   8  Chaining Register CH0-CH3
DMA_DMR1      equ 000DBh  ;  /w   8  Data Mode Register CH4-CH6
DMA_CMR1      equ 000DCh  ;  /w   8  Channel Mode Register CH4-CH6
DMA_CHAIN1    equ 000DDh  ;  /w   8  Chaining Register CH4-CH6
DMA_CMCSR     equ 000DEh  ; r/    8  Chaining Mode Channel Status Reg.
DMA_CBESR     equ 000DFh  ; r/    8  Chaining Base Empty Status Reg.
DMA_IDRSR     equ 0EFE0h  ; r/w   8  Internal DMA Request Sel. Reg.
DMA_CDRR      equ 0EFE1h  ; r/w   8  CPU DMA Request Register

                               ;          (r current, w base)
DMA_BTA0      equ 00000h  ; r/w  16  Base/Curr. Target Address 0
DMA_BTA1      equ 00002h  ; r/w  16  Base/Curr. Target Address 1
DMA_BTA2      equ 00004h  ; r/w  16  Base/Curr. Target Address 2
DMA_BTA3      equ 00006h  ; r/w  16  Base/Curr. Target Address 3
DMA_BTA4      equ 000C0h  ; r/w  16  Base/Curr. Target Address 4
DMA_BTA5      equ 000C4h  ; r/w  16  Base/Curr. Target Address 5

                               ;          (r current, w base)
DMA_BTALP0    equ 00080h  ; r/w   8  Base/Curr. Target Addr. Low Page 0
DMA_BTALP1    equ 00081h  ; r/w   8  Base/Curr. Target Addr. Low Page 1
DMA_BTALP2    equ 00082h  ; r/w   8  Base/Curr. Target Addr. Low Page 2
DMA_BTALP3    equ 00083h  ; r/w   8  Base/Curr. Target Addr. Low Page 3
DMA_BTALP4    equ 00084h  ; r/w   8  Base/Curr. Target Addr. Low Page 4
DMA_BTALP5    equ 00085h  ; r/w   8  Base/Curr. Target Addr. Low Page 5

                               ;          (r current, w base)
DMA_BTAHP0    equ 00018h  ; r/w   8  Base/Curr. Target Addr. High Pg. 0
DMA_BTAHP1    equ 00019h  ; r/w   8  Base/Curr. Target Addr. High Pg. 1
DMA_BTAHP2    equ 0001Ah  ; r/w   8  Base/Curr. Target Addr. High Pg. 2
DMA_BTAHP3    equ 0001Bh  ; r/w   8  Base/Curr. Target Addr. High Pg. 3
DMA_BTAHP4    equ 0001Ch  ; r/w   8  Base/Curr. Target Addr. High Pg. 4
DMA_BTAHP5    equ 0001Dh  ; r/w   8  Base/Curr. Target Addr. High Pg. 5

                               ;          (r current, w base)
DMA_BRA0      equ 00010h  ; r/w  16  Base Requestor Address 0