ns486mri.inc

VRTX 商用嵌入式实时操作系统

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;                                                                        ;
;             Copyright (c) 1995,1996 Microtec Reseach Inc.              ;
;                                                                        ;
;    All rights reserved. Microtec's source code is an unpublished       ;
;    work and the use of a copyright notice does not imply otherwise.    ;
;    This source code contains confidential, trade secret material of'   ;
;    Microtec. Any attempt or participation in deciphering,              ;
;    decoding, reverse engineering or in any way altering the source     ;
;    code is strictly prohibited, unless the prior written consent of    ;
;    Microtec is obtained.                                               ;
;                                                                        ;
;                                                                        ;
;    Module Name:           ns486mri.inc                                 ;
;                                                                        ;
;    Identification:        Version 1.0  ns486mri.inc for NS486SXF       ;
;                                                                        ;
;    Date:                  4/29/96                                      ;
;                                                                        ;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;                                                                        ;
;    This module provides the NS486SXF Eval Board initialization code    ;
;    for the XDM Monitor   											 ;
;
; COPYRIGHT
;
;      (c) 1996 National Semiconductor Corporation
;
;
;
;--------------------------------------------------------------------------
; Port I/O Macros

%*DEFINE(SetRegWord (reg,val))(
   mov  edx,%reg
   mov  ax,%val
   out  dx,ax
)

%*DEFINE(SetRegByte (reg,val))(
   mov  edx,%reg
   mov  al,%val
  out  dx,al
)

;--------------------------------------------------------------------------
;       Program the BIU

;
;               Go to 5V IO mode
;
        %SetRegByte (PM_PMR4,     020h)      ; set SETV bit
        %SetRegByte (PM_PMR3,     000h)      ; clear DRVCON bit
;
;               Start of chip select code
;
        %SetRegByte (BIU_CS_EN,       1)      ;Disable chip selects
;
;               Set up the LOGICAL chip selects
;
        %SetRegWord (BIU_CSBAR2_0,    002f8h) ;CS2 - UART, COM 2 address
        %SetRegWord (BIU_CSBAR2_2,    00000h)
        %SetRegWord (BIU_CSARR2_0,    00007h) 
        %SetRegWord (BIU_CSARR2_2,    00000h)

        %SetRegWord (BIU_CSBAR5_0,    00000h) ;CS5 - PC/104 Memory
        %SetRegWord (BIU_CSBAR5_2,    00400h)
        %SetRegWord (BIU_CSARR5_0,    0ffffh)
        %SetRegWord (BIU_CSARR5_2,    000ffh)

        %SetRegWord (BIU_CSBAR6_0,    00000h) ;CS6 -  PC/104 I/O
        %SetRegWord (BIU_CSBAR6_2,    00000h)
        %SetRegWord (BIU_CSARR6_0,    0ffffh)
        %SetRegWord (BIU_CSARR6_2,    00000h)

        %SetRegWord (BIU_CSBAR7_0,    00000h) ;CS7 - 1st meg of PC/104 Memory
        %SetRegWord (BIU_CSBAR7_2,    00400h)
        %SetRegWord (BIU_CSARR7_0,    0ffffh)
        %SetRegWord (BIU_CSARR7_2,    0000fh)

;
;               Select memory vs. i/o
;
        %SetRegByte (BIU_CS_TYPE,     051h)   ;Select which are memory
;
;               Setup the 16-bit stuff
;
        %SetRegByte (BIU_P16LCSR,     001h)   ;EPROM / FLASH
                                                ;are 16-bit, all PC/104 is 8-bit
                                                ;(CS16/ asserted for 16-bit)
                                                ;UART is 8-bit
;        
;                Set all chip selects as cacheable
;
        %SetRegByte (BIU_CCSR,        0FFh)   

;
;               Set-up timing for chip selects
;
        %SetRegByte (BIU_RBATR,       01Ch)   ;ROM BIOS Timing, RDY not used
                                                ;cacheable 
                                                ;Command delay rq'd for FLASH
                                                ;5 cycle wait for 250ns PROMs
        %SetRegByte (BIU_CSATR1,      0ACh)   ;Logical 1 timing
                                                ;Same as RBATR, for now
                                                ;Logical 2 timing (UART)

        %SetRegByte (BIU_CSATR3,      0BAh)   ;Logical 5 & 6(Standard PC/104)
                                                ;  Command delay

        %SetRegByte (BIU_CSATR4,      00Ah)   ;Logical 7 (1st meg)
                                                ;  Command delay

;
;               Map the logical chip selects to the physical signals.
;
        %SetRegByte (BIU_RBSR,        001h)   ;Flash & EPROM
        %SetRegByte (BIU_ECSSR3,      002h)   ;UART
        %SetRegByte (BIU_ECSSR4,      030h)   ;Standard PC/104 memory & I/O
        %SetRegByte (BIU_ECSSR5,      040h)   ;1st meg PC/104 memory
;
;               Enable the BIU chip selects
;
        %SetRegByte (BIU_CS_EN,       073h)   ;Enable all the used ones

;--------------------------------------------------------------------------
; Enable Cache
        
        mov     eax, cr0                ; control register 0
        and     eax, 0BFFFFFFFh         ; set cacheable bit
        mov     cr0, eax                ; write cr0

;--------------------------------------------------------------------------
; Enable access to interrupt controllers
; also map debug UART IRQ to internal IRQ 3 (com2)

        %SetRegByte (BIU_CONTROL1,    010h)   ;Enable access to ICUs
        %SetRegByte (BIU_CONTROL2,    004h)   ;Set the Global Peripheral Enb
        %SetRegByte (PIC_II3SR,       004h)   ;Internal 3 from E_ERQ2

;--------------------------------------------------------------------------
; Set up the DRAM controller

        %SetRegByte (DRAM_BANK,       000h)   ;Both banks half meg
  	    %SetRegByte (DRAM_MASK0,      0FFh)   ;Mask for 1/2 megabytes
        %SetRegByte (DRAM_MASK1,      0FFh)   ;Mask for 1/2 megabytes
        %SetRegByte (DRAM_ADDR1,      001h)   ;Bank 1 somewhere up there

        %SetRegWord (DRAM_REFRESH,    625)    ;Set for 40MHz. CPU 
                                                ;(just over refresh at 50)
        %SetRegWord (DRAM_RAS,        190h)   ;10 usec at 40 MHz.

        %SetRegWord (DRAM_CONTROL,    0000100110010011b)
                                                ;Parity Error NMI Disabled
                                                ;Bank 1, 9 row addresses
                                                ;Bank 0, 9 row addresses
                                                ;Four Cycle Page Miss
                                                ;Extended CAS Low
                                                ;Normal Refresh
                                                ;Parity Disabled
                                                ;Bank 1 present
                                                ;Bank 0 present


        mov     cx, 1250              ;Should provide 5000 clocks min
dram_count:
        dec     cx
        jnz     dram_count

dram_not_rdy:
        mov     dx,DRAM_STATUS                ;spin until DRAM controler ready
        in      ax,dx
        test    ax,01h
        jz      dram_not_rdy

;--------------------------------------------------------------------------
; end ns486mri.inc
;--------------------------------------------------------------------------