gpif.h

cy68013a USB2.0 highspeed mass storage source code

//-----------------------------------------------------------------------------
//   File:      gpif.h
//   Contents:   Header file
//
// Copyright (c) 1999 Cypress Semiconductor, Inc. All rights reserved
//
// $Archive: /USB/atapifx2/CY4611B/gpif.h $
// $Date: 3/30/05 2:38p $
// $Revision: 2 $
//-----------------------------------------------------------------------------
#include "atapi.h"

#define OUTATAPI  IOA

#define IFCONFIG_UDMA_W  0x82
#define IFCONFIG_UDMA_R  0xC2
#define IFCONFIG_DEFAULT 0xCA
                        // 11001010
                        // ||||||||_0 = IFCFG = GPIF Interface (internal master)
                        // |||||||__1 = IFCFG /
                        // ||||||___0 = Don't output GSTATE on port E
                        // |||||____1 = ASYNC -- Control lines are clocks, not enables
                        // ||||_____0 = IFclock polarity = normal
                        // |||______0 = Disable IFclock Output enable
                        // ||_______1 = 48Mhz IFclock
                        // |________1 = Internal IFclock


// Other ATAPI signals -- Port A
#if REVC_4611_BOARD
   // Mapping of DA and CS numbers to port pins
   #define DA(x)  (x << 1)
   #define CS(x)  (x << 4)

   // Interrupt mapped to WAKEUP.
   #define CF_CE1_               (1<<0)         // Both CE1 and CE0 are active low.  They're both on the same pin.
   #define CF_CE0_               (1<<0)
   #define VBUS_PRESENT          (PA6)
   #define VBUS_PIN              (1<<6)         /* input/output shared w/ ATA_RESET */
   #define ATAPI_RESET_BIT       (1<<6) 
   #define ATAPI_RESET_          PA6
   #define CF_RESET_BIT          (1<<7)         // Shared pin -- Floats high without a card.  Drive high for reset.  Floats low when there's a card.
   #define CF_DETECT_BIT         (1<<7) 
   #define CF_RESET              PA7
   #define CF_DETECT_            PA7

   #define PORTA_OE              0x3F           
   #define ATAPI_IDLE_VALUE      (CF_CE1_ | ATAPI_RESET_BIT | DA(7)|CS(3))
#else
   /////////////////////////////////////////////////////////////////////////
   // PORTA definitions
   // Mapping of DA and CS numbers to port pins
   // The DA mapping is a little tricky here.  The AT2 and AT2LP have different pinouts, so
   // we map DA2 twice:  it appears on PA3 on the AT2 and PA6 on the new board.  The OE bits
   // prevent us from actually having the signal show up twice.
   #define DA(x)  ((x << 1) | ((x << (6-2))&0x40))
   #define CS(x)  (x << 4)

   // Pin 7 -- ATARESET#
   // Pin 6 -- VBUS / DA2
   // Pin 5 -- CS1
   // Pin 4 -- CS0
   // Pin 3 -- DA2 / DRVPWRVALID
   // Pin 2 -- DA1
   // Pin 1 -- DA0
   // Pin 0 -- Interrupt
   #define ATAPI_RESET_BIT       (0x80)
   #define CF_DETECT_            (PA3 ^ bDRVPWRVLD_POLARITY)
   #define ATAPI_IDLE_VALUE      (ATAPI_RESET_BIT | DA(7)|CS(3))
   #define PORTA_OE ((!bNewAt2pinout) ? 0xBE : 0xF6)      /* bBUTTON_PINOUT here is the same in both cases */
   #define ATAPI_RESET_          (PA7)         /* output */
#endif

// Need to keep this #define from the old pinout for compatability
#define VBUS_PRESENT          (PA6)

/////////////////////////////////////////////////////////////////////////
// PORTC definitions
#define nLOWPWR   PC1   /* Active low OUTPUT */
#define DISKRDY   PC4   /* Active high INPUT */
#define VBUSPWRD  PC5   /* Active high INPUT */
#define SYSIRQ (EXIF & (1<<6))

/////////////////////////////////////////////////////////////////////////
// PORTE definitions
#define nPWR500   (1<<0)   /* Active low OUTPUT */
#define ATAPUEN   (1<<1)   /* Active high OUTPUT */
#define GPIOS     IOE
#define GPIO_OE   OEE

#define PORTC_OE           0x0e  
#define PORTC_OE_SUSPEND   0x00
#define PORTE_OE           (bBUTTON_PINOUT ? 0 : 0x03)
#define PORTE_OE_SUSPEND   (bBUTTON_PINOUT ? 0 : nPWR500)

#define USE_IORDY    1

#undef _at_


//-----------------------------------------------------------------------------
// GPIF Globals
//-----------------------------------------------------------------------------

// Port B is ALL GPIF

#define ATAPI_ADDR_MASK       (DA(7)|CS(3))
#define ATAPI_OE              (DA(7)|CS(3))

#define IORDY_TIMEOUT_RELOAD	    200

#define gpifIdle() (GPIFTRIG & 0x80)

// States
#define UNCONFIGURED        0
#define WAIT_FOR_CBW        1
#define RECEIVED_OUT_CMD    2
#define RECEIVED_IN_CMD     3
#define RECEIVED_CBW        4

#define GPIFWFSELECT_DEFAULT ((0 << 6)|(1<<4))    /* FIFO RD / FIFO WR will change on the fly, but the upper half (single) is always the same) */