📄 fx2regs.h
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#define RES_WAVEDATA_END (XBYTE[ 0xE480])
#define CPUCS (XBYTE[ 0xE600])
#define IFCONFIG (XBYTE[ 0xE601])
#define PINFLAGSAB (XBYTE[ 0xE602])
#define PINFLAGSCD (XBYTE[ 0xE603])
#define FIFORESET (XBYTE[ 0xE604])
#define BREAKPT (XBYTE[ 0xE605])
#define BPADDR (XWORD[ 0xe606/2])
#define BPADDRH (XBYTE[ 0xE606])
#define BPADDRL (XBYTE[ 0xE607])
#define UART230 (XBYTE[ 0xE608])
#define FIFOPINPOLAR (XBYTE[ 0xE609])
#define REVID (XBYTE[ 0xE60A])
#define REVCTL (XBYTE[ 0xE60B])
#define EP1OUTCFG (XBYTE[ 0xE610])
#define EP1INCFG (XBYTE[ 0xE611])
#define EP2CFG (XBYTE[ 0xE612])
#define EP4CFG (XBYTE[ 0xE613])
#define EP6CFG (XBYTE[ 0xE614])
#define EP8CFG (XBYTE[ 0xE615])
#define EP2FIFOCFG (XBYTE[ 0xE618])
#define EP4FIFOCFG (XBYTE[ 0xE619])
#define EP6FIFOCFG (XBYTE[ 0xE61A])
#define EP8FIFOCFG (XBYTE[ 0xE61B])
#define EP2AUTOINLENH (XBYTE[ 0xE620])
#define EP2AUTOINLENL (XBYTE[ 0xE621])
#define EP4AUTOINLENH (XBYTE[ 0xE622])
#define EP4AUTOINLENL (XBYTE[ 0xE623])
#define EP6AUTOINLENH (XBYTE[ 0xE624])
#define EP6AUTOINLENL (XBYTE[ 0xE625])
#define EP8AUTOINLENH (XBYTE[ 0xE626])
#define EP8AUTOINLENL (XBYTE[ 0xE627])
#define EP2FIFOPFH (XBYTE[ 0xE630])
#define EP2FIFOPFL (XBYTE[ 0xE631])
#define EP4FIFOPFH (XBYTE[ 0xE632])
#define EP4FIFOPFL (XBYTE[ 0xE633])
#define EP6FIFOPFH (XBYTE[ 0xE634])
#define EP6FIFOPFL (XBYTE[ 0xE635])
#define EP8FIFOPFH (XBYTE[ 0xE636])
#define EP8FIFOPFL (XBYTE[ 0xE637])
#define EP2ISOINPKTS (XBYTE[ 0xE640])
#define EP4ISOINPKTS (XBYTE[ 0xE641])
#define EP6ISOINPKTS (XBYTE[ 0xE642])
#define EP8ISOINPKTS (XBYTE[ 0xE643])
#define INPKTEND (XBYTE[ 0xE648])
#define EP2FIFOIE (XBYTE[ 0xE650])
#define EP2FIFOIRQ (XBYTE[ 0xE651])
#define EP4FIFOIE (XBYTE[ 0xE652])
#define EP4FIFOIRQ (XBYTE[ 0xE653])
#define EP6FIFOIE (XBYTE[ 0xE654])
#define EP6FIFOIRQ (XBYTE[ 0xE655])
#define EP8FIFOIE (XBYTE[ 0xE656])
#define EP8FIFOIRQ (XBYTE[ 0xE657])
#define IBNIE (XBYTE[ 0xE658])
#define IBNIRQ (XBYTE[ 0xE659])
#define NAKIE (XBYTE[ 0xE65A])
#define NAKIRQ (XBYTE[ 0xE65B])
#define USBIE (XBYTE[ 0xE65C])
#define USBIRQ (XBYTE[ 0xE65D])
#define EPIE (XBYTE[ 0xE65E])
#define EPIRQ (XBYTE[ 0xE65F])
#define GPIFIE (XBYTE[ 0xE660])
#define GPIFIRQ (XBYTE[ 0xE661])
#define USBERRIE (XBYTE[ 0xE662])
#define USBERRIRQ (XBYTE[ 0xE663])
#define ERRCNTLIM (XBYTE[ 0xE664])
#define CLRERRCNT (XBYTE[ 0xE665])
#define INT2IVEC (XBYTE[ 0xE666])
#define INT4IVEC (XBYTE[ 0xE667])
#define INTSETUP (XBYTE[ 0xE668])
#define PORTACFG (XBYTE[ 0xE670])
#define PORTCCFG (XBYTE[ 0xE671])
#define PORTECFG (XBYTE[ 0xE672])
#define I2CS (XBYTE[ 0xE678])
#define I2DAT (XBYTE[ 0xE679])
#define I2CTL (XBYTE[ 0xE67A])
#define XAUTODAT1 (XBYTE[ 0xE67B])
#define XAUTODAT2 (XBYTE[ 0xE67C])
#define USBCS (XBYTE[ 0xE680])
#define SUSPEND (XBYTE[ 0xE681])
#define WAKEUPCS (XBYTE[ 0xE682])
#define TOGCTL (XBYTE[ 0xE683])
#define USBFRAMEH (XBYTE[ 0xE684])
#define USBFRAMEL (XBYTE[ 0xE685])
#define MICROFRAME (XBYTE[ 0xE686])
#define FNADDR (XBYTE[ 0xE687])
#define EP0BCH (XBYTE[ 0xE68A])
#define EP0BCL (XBYTE[ 0xE68B])
#define EP1OUTBC (XBYTE[ 0xE68D])
#define EP1INBC (XBYTE[ 0xE68F])
#define EP2BC (XWORD[0xe690/2])
#define EP2BCH (XBYTE[ 0xE690])
#define EP2BCL (XBYTE[ 0xE691])
#define EP4BCH (XBYTE[ 0xE694])
#define EP4BCL (XBYTE[ 0xE695])
#define EP6BCH (XBYTE[ 0xE698])
#define EP6BCL (XBYTE[ 0xE699])
#define EP8BCH (XBYTE[ 0xE69C])
#define EP8BCL (XBYTE[ 0xE69D])
#define EP0CS (XBYTE[ 0xE6A0])
#define EP1OUTCS (XBYTE[ 0xE6A1])
#define EP1INCS (XBYTE[ 0xE6A2])
#define EP2CS (XBYTE[ 0xE6A3])
#define EP4CS (XBYTE[ 0xE6A4])
#define EP6CS (XBYTE[ 0xE6A5])
#define EP8CS (XBYTE[ 0xE6A6])
#define EP2FIFOFLGS (XBYTE[ 0xE6A7])
#define EP4FIFOFLGS (XBYTE[ 0xE6A8])
#define EP6FIFOFLGS (XBYTE[ 0xE6A9])
#define EP8FIFOFLGS (XBYTE[ 0xE6AA])
#define EP2FIFOBCH (XBYTE[ 0xE6AB])
#define EP2FIFOBCL (XBYTE[ 0xE6AC])
#define EP4FIFOBCH (XBYTE[ 0xE6AD])
#define EP4FIFOBCL (XBYTE[ 0xE6AE])
#define EP6FIFOBCH (XBYTE[ 0xE6AF])
#define EP6FIFOBCL (XBYTE[ 0xE6B0])
#define EP8FIFOBCH (XBYTE[ 0xE6B1])
#define EP8FIFOBCL (XBYTE[ 0xE6B2])
#define SUDPTRH (XBYTE[ 0xE6B3])
#define SUDPTRL (XBYTE[ 0xE6B4])
#define SUDPTRCTL (XBYTE[ 0xE6B5])
#define GPIFWFSELECT (XBYTE[ 0xE6C0])
#define GPIFIDLECS (XBYTE[ 0xE6C1])
#define GPIFIDLECTL (XBYTE[ 0xE6C2])
#define GPIFCTLCFG (XBYTE[ 0xE6C3])
#define GPIFADRH (XBYTE[ 0xE6C4])
#define GPIFADRL (XBYTE[ 0xE6C5])
#define GPIFTCB3 (XBYTE[ 0xE6CE])
#define GPIFTCB2 (XBYTE[ 0xE6CF])
#define GPIFTCB1 (XBYTE[ 0xE6D0])
#define GPIFTCB0 (XBYTE[ 0xE6D1])
#define GPIFTCMSW (XWORD[ 0xE6CE/2])
#define GPIFTCLSW (XWORD[ 0xE6D0/2])
#define EP2GPIFFLGSEL (XBYTE[ 0xE6D2])
#define EP2GPIFPFSTOP (XBYTE[ 0xE6D3])
#define EP2GPIFTRIG (XBYTE[ 0xE6D4])
#define EP4GPIFFLGSEL (XBYTE[ 0xE6DA])
#define EP4GPIFPFSTOP (XBYTE[ 0xE6DB])
#define EP4GPIFTRIG (XBYTE[ 0xE6DC])
#define EP6GPIFFLGSEL (XBYTE[ 0xE6E2])
#define EP6GPIFPFSTOP (XBYTE[ 0xE6E3])
#define EP6GPIFTRIG (XBYTE[ 0xE6E4])
#define EP8GPIFFLGSEL (XBYTE[ 0xE6EA])
#define EP8GPIFPFSTOP (XBYTE[ 0xE6EB])
#define EP8GPIFTRIG (XBYTE[ 0xE6EC])
#define XGPIFSGLDATH (XBYTE[ 0xE6F0])
#define XGPIFSGLDATLX (XBYTE[ 0xE6F1])
#define XGPIFSGLDATLNOX (XBYTE[ 0xE6F2])
#define GPIFREADYCFG (XBYTE[ 0xE6F3])
#define GPIFREADYSTAT (XBYTE[ 0xE6F4])
#define GPIFABORT (XBYTE[ 0xE6F5])
#define FLOWSTATE (XBYTE[ 0xE6C6])
#define FLOWLOGIC (XBYTE[ 0xE6C7])
#define FLOWEQ0CTL (XBYTE[ 0xE6C8])
#define FLOWEQ1CTL (XBYTE[ 0xE6C9])
#define FLOWHOLDOFF (XBYTE[ 0xE6CA])
#define FLOWSTB (XBYTE[ 0xE6CB])
#define FLOWSTBEDGE (XBYTE[ 0xE6CC])
#define FLOWSTBHPERIOD (XBYTE[ 0xE6CD])
#define GPIFHOLDAMOUNT (XBYTE[ 0xE60C])
#define UDMACRCH (XBYTE[ 0xE67D])
#define UDMACRCL (XBYTE[ 0xE67E])
#define UDMACRCQUAL (XBYTE[ 0xE67F])
#define DBUG (XBYTE[ 0xE6F8])
#define TESTCFG (XBYTE[ 0xE6F9])
#define USBTEST (XBYTE[ 0xE6FA])
#define CT1 (XBYTE[ 0xE6FB])
#define CT2 (XBYTE[ 0xE6FC])
#define CT3 (XBYTE[ 0xE6FD])
#define CT4 (XBYTE[ 0xE6FE])
#define SETUPDAT (XBYTE+0xE6B8)
#define EP0BUF (XBYTE+0xE740)
#define EP1OUTBUF (XBYTE+0xE780)
#define EP1INBUF (XBYTE+0xE7C0)
#define EP2FIFOBUF (XBYTE+0xF000)
#define EP4FIFOBUF (XBYTE+0xF400)
#define EP6FIFOBUF (XBYTE+0xF800)
#define EP8FIFOBUF (XBYTE+0xFC00)
/*-----------------------------------------------------------------------------
Special Function Registers (SFRs)
The byte registers and bits defined in the following list are based
on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
If you modify the register definitions below, please regenerate the file
"ezregs.inc" which includes the same basic information for assembly inclusion.
-----------------------------------------------------------------------------*/
sfr IOA = 0x80;
sbit PA0 = 0x80;
sbit PA1 = 0x81;
sbit PA2 = 0x82;
sbit PA3 = 0x83;
sbit PA4 = 0x84;
sbit PA5 = 0x85;
sbit PA6 = 0x86;
sbit PA7 = 0x87;
sfr SP = 0x81;
sfr DPL = 0x82;
sfr DPH = 0x83;
sfr DPL1 = 0x84;
sfr DPH1 = 0x85;
sfr DPS = 0x86;
/* DPS */
// sbit SEL = 0x86+0;
sfr PCON = 0x87; /* PCON */
//sbit IDLE = 0x87+0;
//sbit STOP = 0x87+1;
//sbit GF0 = 0x87+2;
//sbit GF1 = 0x87+3;
//sbit SMOD0 = 0x87+7;
sfr TCON = 0x88;
/* TCON */
sbit IT0 = 0x88+0;
sbit IE0 = 0x88+1;
sbit IT1 = 0x88+2;
sbit IE1 = 0x88+3;
sbit TR0 = 0x88+4;
sbit TF0 = 0x88+5;
sbit TR1 = 0x88+6;
sbit TF1 = 0x88+7;
sfr TMOD = 0x89;
/* TMOD */
//sbit M00 = 0x89+0;
//sbit M10 = 0x89+1;
//sbit CT0 = 0x89+2;
//sbit GATE0 = 0x89+3;
//sbit M01 = 0x89+4;
//sbit M11 = 0x89+5;
//sbit CT1 = 0x89+6;
//sbit GATE1 = 0x89+7;
sfr TL0 = 0x8A;
sfr TL1 = 0x8B;
sfr TH0 = 0x8C;
sfr TH1 = 0x8D;
sfr CKCON = 0x8E;
/* CKCON */
//sbit MD0 = 0x89+0;
//sbit MD1 = 0x89+1;
//sbit MD2 = 0x89+2;
//sbit T0M = 0x89+3;
//sbit T1M = 0x89+4;
//sbit T2M = 0x89+5;
sfr SPC_FNC = 0x8F; // Was WRS in Reg320
/* CKCON */
//sbit WRS = 0x8F+0;
sfr IOB = 0x90;
sbit PB0 = 0x90;
sbit PB1 = 0x91;
sbit PB2 = 0x92;
sbit PB3 = 0x93;
sbit PB4 = 0x94;
sbit PB5 = 0x95;
sbit PB6 = 0x96;
sbit PB7 = 0x97;
sfr EXIF = 0x91; // EXIF Bit Values differ from Reg320
/* EXIF */
#define bmUSBINT (1 << 4)
#define bmI2CINT (1 << 5)
#define bmIE4 (1 << 6)
#define bmIE5 (1 << 7)
sfr MPAGE = 0x92;
sfr SCON0 = 0x98;
/* SCON0 */
sbit RI = 0x98+0;
sbit TI = 0x98+1;
sbit RB8 = 0x98+2;
sbit TB8 = 0x98+3;
sbit REN = 0x98+4;
sbit SM2 = 0x98+5;
sbit SM1 = 0x98+6;
sbit SM0 = 0x98+7;
sfr SBUF0 = 0x99;
sfr AUTOPTR1H = 0x9A;
sfr AUTOPTR1L = 0x9B;
sfr AUTOPTRH2 = 0x9D;
sfr AUTOPTRL2 = 0x9E;
sfr IOC = 0xA0;
sbit PC0 = 0xa0;
sbit PC1 = 0xa1;
sbit PC2 = 0xa2;
sbit PC3 = 0xa3;
sbit PC4 = 0xa4;
sbit PC5 = 0xa5;
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