start167.166

This example program shows how to configure and use the A/D Converter of the following microcontroll

$MOD167                                 ; Define C167 mode
;
;------------------------------------------------------------------------------
;  This file is part of the C166 Compiler package
;  Copyright KEIL ELEKTRONIK GmbH 1993 - 2004
;  Version 5.01
;------------------------------------------------------------------------------
;  START167.A66:  This code is executed after processor reset and provides the
;                 startup sequence for the extended 166 architecture CPU's.
;                 (i.e. C167/C165/C164/C163/C161, ST10-168/262/269 ect.)
;
;  To translate this file use A166 with the following invocation:
;
;     A166 START167.A66 SET (<model>)
;
;     <model> determines the memory model and can be one of the following:
;         TINY, SMALL, COMPACT, HCOMPACT, MEDIUM, LARGE, HLARGE, XLARGE
;
;  Example:  A166 START167.A66 SET (SMALL)
;
;  To link the modified START167.OBJ file to your application use the following
;  L166 invocation:
;
;     L166 <your object file list>, START167.OBJ <controls>
;
;------------------------------------------------------------------------------
; Setup model-dependend Assembler controls
$CASE
$IF NOT TINY
$SEGMENTED
$ENDIF
;------------------------------------------------------------------------------
;
; Definitions for BUSCON0 and SYSCON Register:
; --------------------------------------------
;
; MCTC0: Memory Cycle Time (BUSCON0.0 .. BUSCON0.3):
; Note: if RDYEN0 == 1 a maximum number of 7 waitstates can be selected
_MCTC0   EQU    1       ; Memory wait states is 1 (MCTC0 field = 0EH).
;                       ; (Reset Value = 15 additional state times)
;
; RWDC0: Read/Write Signal Delay (BUSCON0.4):
_RWDC0   EQU    0       ; 0 = Delay Time     0.5 States (Reset Value)  
;                       ; 1 = No Delay Time  0   States
;
; MTTC0: Memory Tri-state Time (BUSCON0.5):
_MTTC0   EQU    1       ; 0 = Delay Time     1   States (Reset Value)
;                       ; 1 = No Delay Time  0   States
;
$SET (BTYP_ENABLE = 0)  ; 0 = BTYP0 and BUSACT0 is set according to the level
                        ;     at pins P0L.6, P0L.7, and EA# during reset.
                        ; 1 = the following _BTYP0 and _BUSACT0 values are
                        ;     written to BTYP0 and BUSACT0
;
; BTYP0: External Bus Configuration Control (BUSCON0.6 .. BUSCON0.7):
_BTYP0   EQU    2       ; 0 = 8 Bit Non Multiplexed
;                       ; 1 = 8 Bit Multiplexed
;                       ; 2 = 16 Bit Non Multiplexed
;                       ; 3 = 16 Bit Multiplexed
;
; ALECTL0: ALE Lengthening Control Bit (BUSCON0.9):
_ALECTL0 EQU    0       ; see data sheet for description
;
; BUSACT0: Bus Active Control Bit (BUSCON0.10):
_BUSACT0 EQU    1       ; = 0 external bus disabled
                        ; = 1 external bus enabled
;
; RDYEN0: READY# Input Enable control bit (BUSCON0.12):
_RDYEN0  EQU    0       ; 0 = READY# function disabled  (Reset Value)
;                       ; 1 = READY# function enabled
;
; RDY_AS0: Synchronous / Asynchronous READY# Input (BUSCON0.3):
; Note: This bit is only valid if _RDYEN0 == 1.
_RDY_AS0 EQU    0       ; 0 = synchronous READY# input
;                       ; 1 = asynchronous READY# input
;
; CSREN0: Read Chip Select Enable bit (BUSCON0.14, only in some devices):
_CSREN0  EQU    0       ; 0 = CS0# is independent of read command (RD#)
;                       ; 1 = CS0# is generated for the duration of read
;
; CSWEN0: Write Chip Select Enable bit (BUSCON0.15, only in some devices):
_CSWEN0  EQU    0       ; 0 = CS0# is independent of write command (WR#)
;                       ; 1 = CS0# is generated for the duration of write
;
; XPERSHARE: XBUS Peripheral Share Mode Control (SYSCON.0)
_XPERSHARE EQU 0        ; 0 = External accesses to XBUS peripherals disabled
;                       ; 1 = XBUS accessible via external BUS in hold mode
;
; VISIBLE: Visible Mode Control (SYSCON.1)
_VISIBLE EQU 0          ; 0 = Accesses to XBUS are done internally
;                       ; 1 = XBUS accesses are made visible on external pins
;
; XPEN: XRAM & XBUS Peripheral Enable Control Bit (SYSCON.2)
_XPEN   EQU     0       ; 0 = access to on-chip XRAM & XBUS disable => EXT.BUS
;                       ; 1 = on-chip XRAM & XBUS is accessed
;
; BDRSTEN: Bidirectional Reset Enable Bit (SYSCON.3, only in some devices)
_BDRSTEN EQU    0       ; 0 = Pin RSTIN# is an input only
;                       ; 1 = RSTIN# is pulled low during internal reset
;
$SET (OWDDIS_ENABLE = 0); 0 = OWDDIS is set according to the inverted level
;                       ;     at pin RD\ duirng reset.
;                       ; 1 = the following _OWDDIS value is
;                       ;     written to OWDDIS in the SYSCON register
; OWDDIS: Oscillator Watchdog Disable Bit (SYSCON.4, only in some devices)
_OWDDIS EQU     0       ; 0 = the on-chip oscillator watchdog is enabled 
;                       ; 1 = the on-chip oscillator watchdog is disabled
;
; PWDCFG: Power Down Mode Configuration Bit (SYSCON.5, only in some devices)
_PWDCFG EQU     0       ; 0 = Power Down mode can be left via reset
;                       ; 1 = Power Down mode left via ext. or RTC interrupt
;
; CSCFG: Chip Select Configuration Control (SYSCON.6, only in some devices)
_CSCFG  EQU     0       ; 0 = Latched CS mode; CS signals are latch internally
;                       ; 1 = Unlatched CS mode
; 
$SET (WRCFG_ENABLE = 0) ; 0 = WRCFG is set according to the level at
;                       ;     pin P0H.0 during reset.
;                       ; 1 = the following _WRCFG value is
;                       ;     written to WRCFG in the SYSCON register
; WRCFG: Write Configuration Control Bit (SYSCON.7):
_WRCFG   EQU    0       ; 0 = Normal configuration of WR# and BHE#
;                       ; 1 = WR# pin acts as WRL#, BHE# pin acts as WRH#
;
; CLKEN: System Clock Output Enable bit (SYSCON.8):
_CLKEN  EQU     0       ; 0 = disabled    (Reset Value)
;                       ; 1 = enabled
;
; BYTDIS: Byte High Enable pin control bit (SYSCON.9):
_BYTDIS EQU     0       ; 0 = enabled     (Reset Value)
;                       ; 1 = disabled
;
$SET (ROMEN_ENABLE = 0) ; 0 = ROMEN is set according to the level at
;                       ;     pin EA# during reset.
;                       ; 1 = the following _ROMEN value is
;                       ;     written to ROMEN in the SYSCON register
; ROMEN: Internal ROM Access Enable control bit (SYSCON.10):
_ROMEN  EQU     0       ; 0 = Internal ROM disabled
                        ; 1 = Internal ROM enabled
;
; SGTDIS: Segmentation Disable control bit (SYSCON.11):
$IF TINY
_SGTDIS EQU     1       ; disable segmented mode for TINY model
$ELSE
_SGTDIS EQU     0       ; enable segmented mode (Reset Value)
$ENDIF
;
; ROMS1: ROM Segment Mapping Control Bit (SYSCON.12):
_ROMS1  EQU     0       ; _ROMS1 = 0 Internal ROM mapped to segment 0
;                       ; _ROMS1 = 1 Internal ROM mapped to segment 1
;
; STKSZ: Maximum System Stack Size selection  (SYSCON.13 .. SYSCON.15)
;  Defines the system stack space which is used by CALL/RET and PUSH/POP
;  instructions.  The system stack space must be adjusted according the
;  actual requirements of the application.
$SET (STK_SIZE = 0)
;     System stack sizes:
;       0 = 256 words (Reset Value)
;       1 = 128 words
;       2 =  64 words
;       3 =  32 words
;       4 = 512 words
;       5 = not implemented
;       6 = not implemented
;       7 = no wrapping (entire internal RAM use as STACK, set size with SYSSZ)
; If you have selected 7 for STK_SIZE, you can set the actual system stack size
; with the following SSTSZ statement.
SSTSZ   EQU     200H    ; set System Stack Size to 200H Bytes
;
; USTSZ: User Stack Size Definition 
;  Defines the user stack space available for automatics.  This stack space is
;  accessed by R0.  The user stack space must be adjusted according the actual
;  requirements of the application.
USTSZ   EQU     200H    ; set User Stack Size to 200H Bytes.
;
; WATCHDOG: Disable Hardware Watchdog
; --- Set WATCHDOG = 1 to enable the Hardware watchdog
$SET (WATCHDOG = 0)
;
;
; CLR_MEMORY: Disable Memory Zero Initialization of RAM area
; --- Set CLR_MEMORY = 0 to disable memory zero initilization
$SET (CLR_MEMORY = 1)
;
; INIT_VARS: Disable Variable Initialization
; --- Set INIT_VARS = 0 to disable variable initilization
$SET (INIT_VARS = 1)
;
; DPPUSE:  Re-assign DPP registers
; --- Set DPPUSE = 0 to reduce the code size of the startup code, if you
;                    are not using the L166 DPPUSE directive.
$SET (DPPUSE = 1)
;
; DPP3USE: Use DPP3 register during variable initilization
; --- Set DPP3USE = 0 to disable the usage of DPP3 during initilization of
;                     variables.  This option might be required if you write
;                     program parts that are reloaded during application 
;                     execution and increase code size of the startup code.
$SET (DPP3USE = 1)
;
;------------------------------------------------------------------------------
; Initialization for XPERCON register (available on some derivatives only)
;
; INIT_XPERCON: Init XPERCON register available on some devices
; --- Set INIT_XPERCON = 1 to initilize the XPERCON register
$SET (INIT_XPERCON = 0)
;
; Note: The verious devices of 166/ST10 family provide different XPERCON
;       registers.  Therefore you can set a fixed XPERCON value with the
;       following EQU statment.  Please consult the Microcontroller 
;       User's Guide for the exact definition of the XPERCON SFR in your
;       166/ST10 derivative.
;
;            Bit  15   11    7    3
V_XPERCON  EQU     0000$0000$0000$0000B   ; XPERCON values
;
; XPERCON Bits in various devices (Note: not all devices are listed)
;   C165UTAH:  Bit 5: IOM-2, Bit 6: USB,  Bit 7:  EPEC
;   C167CS:    Bit 0: CAN1,  Bit 1: CAN2, Bit 10: XRAM 2K  Bit 11: XRAM 6K
;
;------------------------------------------------------------------------------
;
; Initialization for SYSCON2 and SYSCON3 (available on some derivatives only)
; Note: The SYSCON2 and SYSCON3 bits may be different in some derivatives.
;       Check the values carefully!
;
; ADVANCED_SYSCON: Init SYSCON2 and SYSCON3 register available on some devices
; --- Set ADVANCE_SYSCON = 1 to initilize SYSCON2 and SYSCON3
$SET (ADVANCED_SYSCON = 0)
;
; --- SYSCON2 values
;
; PDCON: Power Down Control (during power down mode) (SYSCON2.4 .. SYSCON2.5)
PDCON   EQU     0       ; 0 = RTC On,  Ports On  (default after Reset)
;                       ; 1 = RTC On,  Ports Off
;                       ; 2 = RTC Off, Ports On
;                       ; 3 = RTC Off, Ports Off
;
; RTS: RTC Clock Source (not affected by a reset) (SYSCON2.6)
RTS     EQU     0       ; 0 = Main oscillator
;                       ; 1 = Auxiliary oscillator (if available)
;
; SCS: SDD Clock Source (not affected by a reset) (SYSCON2.7)
SCS     EQU     0       ; 0 = Main oscillator
;                       ; 1 = Auxiliary oscillator (if available)
;
; CLKCON: Clock State Control (SYSCON2.8 .. SYSCON2.9)
CLKCON  EQU     0       ; 0 = Running on configured basic frequency
;                       ; 1 = Running on slow down frequency, PLL ON
;                       ; 2 = Running on slow down frequency, PLL OFF
;                       ; 3 = reserved
;
; CLKREL: Reload Counter Value for Slowdown Devider (SYSCON2.10 .. SYSCON2.14)
CLKREL  EQU     0       ; possible values are 0 .. 31
;
;
; --- SYSCON3 values: disable on-chip peripherals
;
ADCDIS  EQU     0       ; 1 = disable Analog/Digital Converter    (SYSCON3.0)
ASC0DIS EQU     0       ; 1 = disable UART ASC0                   (SYSCON3.1)
SSCDIS  EQU     0       ; 1 = disable Synchronus Serial Cnl SSC   (SYSCON3.2)
GPTDIS  EQU     0       ; 1 = disable Timer Block GPT             (SYSCON3.3)
                        ; reserved                                (SYSCON3.4)
FMDIS   EQU     0       ; 1 = disable on-chip Flash Memory Module (SYSCON3.5)
CC1DIS  EQU     0       ; 1 = disable CAPCOM Unit 1               (SYSCON3.6)
CC2DIS  EQU     0       ; 1 = disable CAPCOM Unit 2               (SYSCON3.7)
CC6DIS  EQU     0       ; 1 = disable CAPCOM Unit 6               (SYSCON3.8)
PWMDIS  EQU     0       ; 1 = disable Pulse Width Modulation Unit (SYSCON3.9)
ASC1DIS EQU     0       ; 1 = disable UART ASC1                   (SYSCON3.10)
I2CDIS  EQU     0       ; 1 = disable I2C Bus Module              (SYSCON3.11)
;                       ; reserved                                (SYSCON3.12)
CAN1DIS EQU     0       ; 1 = disable on-chip CAN Module 1        (SYSCON3.13)
CAN2DIS EQU     0       ; 1 = disable on-chip CAN Module 2        (SYSCON3.14)
PCDDIS  EQU     0       ; 1 = disable Peripheral Clock Driver     (SYSCON3.15)
;
;------------------------------------------------------------------------------
; Initialization for RSTCON register (available on some derivatives only)
;
; INIT_RSTCON: Init RSTCON register available on some devices
; --- Set INIT_RSTCON = 1 to initilize the RSTCON register
$SET (INIT_RSTCON = 0)
;
; --- RSTCON values
;
; R_RSTLEN: Reset Length Control (duration of next reset; RSTCON.0 .. RSTCON.1)
R_RSTLEN   EQU     0       ; 0 = 1024 TCL:  standard duration
;                          ; 1 = 2048 TCL:  extended duration
;
; R_SUE: Software Update enable (RSTCON.8)
R_SUE      EQU     0       ; 0 = Configuration cannot be changed (default)
;                          ; 1 = Software update of configuration is enabled
;
; R_CSSEL: Chip Select Lines (number of CS pins; RSTCON.9 .. RSTCON.10)
R_CSSEL    EQU     0       ; 0 = 3 CS lines (CS2# .. CS0#) (default)
;                          ; 1 = 2 CS lines (CS1# .. CS0#)
;                          ; 2 = No CS lines at all
;                          ; 3 = all CS lines (CSx# .. CS0#)                
;
; R_SALSEL: Segment Address Lines (number of address pins; RSTCON.11 .. RSTCON.12)
R_SALSEL   EQU     0       ; 0 = 4-bit segment address: A19 .. A16 (default)
;                          ; 1 = No segment address lines at all
;                          ; 2 = full segment address:  Axx .. A16
;                          ; 3 = 2-bit segment address: A17 .. A16
;
; R_CLKCFG: Clock Generation Mode (XTAL PLL factor; RSTCON.13 .. RSTCON.15)
R_CLKCFG   EQU     0       ; 0 = CPU CLOCK = XTAL * 2.5
;                          ; 1 = CPU CLOCK = XTAL / 2.0