startup.s

S3C3410X(arm7tdmi)移植代码

;;	P8.7  P8.6  P8.5  P8.4  P8.3  P8.2  P8.1  P8.0
;;	IN    IN    IN    IN    IN    IN    IN    IN
;;      0     0     0     0     0     0     0     0	(0000 0000)
;;	UP    UP    UP	  UP    UP    UP    UP    UP	(1111 1111)

	ldr	r1,	=PCON8
	ldr	r0,	=0x0
	strb	r0,	[r1]

	ldr	r1,	=PUR8
	ldr	r0,	=0xff
	strb	r0,	[r1]

; **********************************************************************
; *	s3c3410x 俊绰 Clock Controller 啊 绝栏骨肺 力芭茄促.	       *
; **********************************************************************
;	ldr	r0,=CLKCON		 
;	ldr	r1,=0x3ff8		;All unit block CLK enable	
;	str	r1,[r0]
	
; **********************************************************************
; *			Configuration memory allocation		       *
; *		This operation must be performed immediately	       *
; **********************************************************************

;	ldr	r0,=SMRDATA	; Load address of area 'SMRDATA'
;	ldmia	r0,{r1-r11}	; Load each word value of 'SMRDATA'
;	ldr	r0,=0x01c80000	; BWSCON Address
;	stmia	r0,{r1-r11}	; Store each 'SMRDATA' value 
				;       to the system manager registers
; ---------------------------------------------------------------------
; 盔贰 内靛(困)甫 酒贰贸烦 荐沥沁促.
; ---------------------------------------------------------------------
	ldr	r0,=SMRDATA	; Load address of area 'SMRDATA'
	ldmia	r0,{r1-r11}	; Load each word value of 'SMRDATA'
	ldr	r0,=MEMCON0	; MEMBANK0 offset : 0x2000
	stmia	r0,{r1-r11}	; Store each 'SMRDATA' value 
				;       to the system manager registers

; ---------------------------------------------------------------------

	ldr sp, =SVCStack	; Why?

	bl InitStacks

	ldr	r0,=HandleIRQ
	ldr	r1,=IsrIRQ
	str	r1,[r0]

;; ---------------------------------------------------------------------
;; Initialization for C source program
;; ---------------------------------------------------------------------
;; Initialize memory required for C code
;;   - RAM initialization
;;   - Copy all read / write data from Assembler & C code to 
;;	the read / write area
;;   - Copy Zero initialized data from C code to the read/write area
;;	(for example, global variable)
;; ---------------------------------------------------------------------

	LDR	r0, =|Image$$RO$$Limit| ; Get pointer to ROM data
	LDR	r1, =|Image$$RW$$Base|	; and RAM copy
	LDR	r3, =|Image$$ZI$$Base|	
	;Zero init base => top of initialised data
			
	CMP	r0, r1					; Check that they are different
	BEQ	%F1
0		
	CMP	r1, r3					; Copy init data
	LDRCC	r2, [r0], #4
	STRCC	r2, [r1], #4
	BCC	%B0
1		
	LDR	r1, =|Image$$ZI$$Limit| ; Top of zero init segment
	MOV	r2, #0
2		
	CMP	r3, r1					; Zero init
	STRCC	r2, [r3], #4
	BCC	%B2


;---------------------------------------------------------------------
; Thumb mode 甫 荤侩窍瘤 臼绰促.
; 弊矾骨肺, Thumb mode 甫 备盒窍绰 何盒阑 林籍贸府茄促.
;---------------------------------------------------------------------
	BL	Main		    ;Don't use main() because ......
	B	.
	
;---------------------------------------------------------------------
; 盔贰 乐带 内靛... 酒贰 何盒阑 困贸烦 荐沥沁澜.
;	[ :LNOT:THUMBCODE
;	BL	Main		    ;Don't use main() because ......
;	B	.						
;	]
;
;	[ THUMBCODE		    ;for start-up code for Thumb mode
;        orr     lr,pc,#1
;        bx      lr
;        CODE16
;        bl      Main                ;Don't use main() because ......
;        b       .
;        CODE32
;	]


; **********************************************************************
; *			胶琶 檬扁拳 风凭			       *
; **********************************************************************
InitStacks
	;Don't use DRAM,such as stmfd,ldmfd......
	;SVCstack is initialized before
	;Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
	
	mrs	r0,cpsr
	bic	r0,r0,#MODEMASK
	orr	r1,r0,#UNDEFMODE|NOINT
	msr	cpsr_cxsf,r1 				;UndefMode
	ldr	sp,=UndefStack
;; ----------------------------------------------------
	orr	r1,r0,#ABORTMODE|NOINT
	msr	cpsr_cxsf,r1 				;AbortMode
	ldr	sp,=AbortStack
;; ----------------------------------------------------
	orr	r1,r0,#IRQMODE|NOINT
	msr	cpsr_cxsf,r1 				;IRQMode
	ldr	sp,=IRQStack
;; ----------------------------------------------------
	orr	r1,r0,#FIQMODE|NOINT
	msr	cpsr_cxsf,r1 				;FIQMode
	ldr	sp,=FIQStack
;; ----------------------------------------------------
	bic	r0,r0,#MODEMASK|NOINT
	orr	r1,r0,#SVCMODE
	msr	cpsr_cxsf,r1 				;SVCMode
	ldr	sp,=SVCStack
;; ----------------------------------------------------
	;USER mode is not initialized.

	mov	pc,lr 
	
	;The LR register may be not valid for the mode changes.

; **********************************************************************
; *			Entering Stop mode			       *
; **********************************************************************
;; ---------------------------------------------------------------------
;; void EnterPWDN(int CLKCON);
;; EnterPWDN() has to be on ROM(0~0x1fffff) for DRAM self-refresh
;; ---------------------------------------------------------------------

EnterPWDN
	mov	r10,r0

        nop     ;Wait until self-refresh is issued. May not be needed.
        nop     ;If the other bus master holds the bus, ...
        nop
        nop
        nop
        nop
        nop

        ;enter POWERDN mode;
	ldr	r0,=SYSCON
	strb	r10,[r0]

        ;wait until enter STOP mode and until wake-up
	mov	r0,#0xff
0       subs    r0,r0,#1
	bne	%B0

	mov	pc,	lr

	LTORG

; ----------------------------------------------------------------------
; 盔贰 乐带 内靛甫 林籍贸府 窍看促.
; ----------------------------------------------------------------------
;void EnterPWDN(int CLKCON);
;EnterPWDN() has to be on ROM(0~0x1fffff) for DRAM self-refresh


;EnterPWDN
;	mov	r2,r0
	
	;enter DRAM/SDRAM self refresh mode.
;	ldr	r0,=DRAMCON
;	ldr	r3,[r0]
;        bic     r3,r3,#0x1e0000
        
;	[ BDRAMTYPE="DRAM"
;        orr     r3,r3,#0x80000 ;If DRAM is LATCH mode,
;	mov	r1,r3
;	bic     r1,r1,#0x10
;	| ;"SDRAM"
;	orr     r3,r3,#0x100000 ;If SDRAM is LATCH mode,
;	mov	r1,r3
;        orr     r1,r1,#0x10000
;        bic     r1,r1,#0x10
;        ]
;	str	r1,[r0]

;        nop     ;Wait until self-refresh is issued. May not be needed.
;        nop     ;If the other bus master holds the bus, ...
;        nop
;        nop
;        nop
;        nop
;        nop

        ;enter POWERDN mode
;	ldr	r0,=CLKCON
;	str	r2,[r0]

        ;wait until enter SL_IDLE,STOP mode and until wake-up
;	mov	r0,#0xff 
;0       subs    r0,r0,#1
;	bne	%B0

	;exit from DRAM/SDRAM self refresh mode.
;	ldr	r0,=DRAMCON
;        str     r3,[r0]

;	mov pc,lr

;LTORG

;*********************************************************************
;*		矫胶袍 皋葛府甫 汲沥茄促.			     *
;*	(盔贰 家胶俊档 捞 何盒俊 秦寸窍绰 内靛啊 乐菌瘤父, 	     *
;*	  呈公 辨绊 瘤历盒 秦辑 昏力 沁促.)			     *
;*********************************************************************
;; ---------------------------------------------------------------------
;; System Initialization Setting
;; ---------------------------------------------------------------------
;; Memory configuration has to be optimized for best performance
;; The following parameter is not optimized.
;; Memory access cycle parameter strategt
;;   - Even FP-DRAM, EDO DRAM setting has more late fetch point by 
;;	half-clock
;;   - The memory setting, here, are made the safe parameters even at 
;;	25MHz
;;   - FP-DRAM parameter : 
;;   - DRAM refresh rate is for 25MHz
;; ---------------------------------------------------------------------
SyscfgDataSdram
	DCD MEMORY0_SDRAM + SYSCFG_0KB + SFR_STARTADDRESS
	ALIGN

SyscfgDataEdoDram
	DCD MEMORY0_EDO + SYSCFG_4KB + SFR_STARTADDRESS + CACHE_ON + WRBUF_ON
	ALIGN

SMRDATA
	DCD (0x8<<21) + (0x0<<10) + TACP_5 + TACC_4 + SM_NO_16_SRAM + PMC_SINGLE + DBW_16
	DCD 0x0						; Bank1=Disable
	DCD 0x0						; Bank2=Disable
	DCD 0x0						; Bank3=Disable
	DCD 0x0						; Bank4=Disable
	DCD 0x0						; Bank5=Disable
	[ DRAMTYPE = "SDRAM"
	DCD (0x200<<21) + (0x100<<10) + TRP_2 + TRC_2 + CAN_8 + DBW_16
	|	;; "DRAM"
	DCD (0x200<<21) + (0x100<<10) + TRP_3 + TRC_2 + TCAS_2 + TCP_1 + CAN_10 + DBW_16
	]
	DCD 0x0						; Bank7=Disable
	DCD (0x4f5<<1) + VSMR_1 + REFRESH_ON + TCH_2 + TCSR_1
	ALIGN
;; ---------------------------------------------------------------------


	AREA RamData, DATA, READWRITE

	^	(_ISR_STARTADDRESS-0x500)  ;0x1000 俊辑 0x500 栏肺 函版
				
;UserStack	#	256
SVCStack	#	256
UndefStack	#	256
AbortStack	#	256
IRQStack	#	256
FIQStack	#	256



		^	_ISR_STARTADDRESS
HandleReset	#	   4
HandleUndef	#	   4
HandleSWI	#	   4
HandlePabort	#	   4
HandleDabort	#	   4
HandleReserved	#	   4
HandleIRQ	#	   4
HandleFIQ	#	   4

;Don't use the label 'IntVectorTable',
;because armasm.exe cann't recognize this label correctly.
;the value is different with an address you think it may be.
;IntVectorTable


IntVectorTable
HandleEINT0	#	4
HandleEINT1	#	4
HandleURX	#	4
HandleUTX	#	4
HandleUERR	#	4
HandleDMA0	#	4
HandleDMA1	#	4
HandleTOF0	#	4
HandleTMC0	#	4
HandleTOF1	#	4
HandleTMC1	#	4
HandleTOF2	#	4
HandleTMC2	#	4
HandleTOF3	#	4
HandleTMC3	#	4
HandleTOF4	#	4
HandleTMC4	#	4
HandleBT	#	4
HandleSIO0	#	4
HandleSIO1	#	4
HandleIIC	#	4
HandleRTCA	#	4
HandleRTCT	#	4
HandleTF	#	4
HandleEINT2	#	4
HandleEINT3	#	4
HandleEINT4	#	4
HandleADC	#	4
HandleEINT8	#	4
HandleEINT9	#	4
HandleEINT10	#	4
HandleEINT11	#	4
HandleUnused	#	20

;-----------------------------------------------------------------------
;林籍贸府
;-----------------------------------------------------------------------
;HandleADC	#	   4
;HandleRTC	#	   4
;HandleUTXD1	#	   4
;HandleUTXD0	#	   4
;HandleSIO	#	   4
;HandleIIC	#	   4
;HandleURXD1	#	   4
;HandleURXD0	#	   4
;HandleEINT67	#	   4
;HandleWDT	#	   4
;HandleTIMER3	#	   4
;HandleTIMER2	#	   4
;HandleTIMER1	#	   4
;HandleTIMER0	#	   4
;HandleUERR1	#	   4
;HandleUERR0	#	   4
;HandleBDMA1	#	   4
;HandleBDMA0	#	   4
;HandleZDMA1	#	   4
;HandleZDMA0	#	   4
;HandleEINT5	#	   4
;HandleEINT4	#	   4
;HandleEINT3	#	   4
;HandleEINT2	#	   4
;HandleEINT1	#	   4
;HandleEINT0	#	   4   ;0xc7fff84

		END