tl16pir552.c

JAPAN RTOS TOPPERS/JSP kernel 1.4 PreRelease simulation environment JSP kernel Windows simulation

/*
 *  TOPPERS/JSP Kernel
 *      Toyohashi Open Platform for Embedded Real-Time Systems/
 *      Just Standard Profile Kernel
 * 
 *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
 *                              Toyohashi Univ. of Technology, JAPAN
 * 
 *  忋婰挊嶌尃幰偼丆埲壓偺 (1)乣(4) 偺忦審偐丆Free Software Foundation 
 *  偵傛偭偰岞昞偝傟偰偄傞 GNU General Public License 偺 Version 2 偵婰
 *  弎偝傟偰偄傞忦審傪枮偨偡応崌偵尷傝丆杮僜僼僩僂僃傾乮杮僜僼僩僂僃傾
 *  傪夵曄偟偨傕偺傪娷傓丏埲壓摨偠乯傪巊梡丒暋惢丒夵曄丒嵞攝晍乮埲壓丆
 *  棙梡偲屇傇乯偡傞偙偲傪柍彏偱嫋戻偡傞丏
 *  (1) 杮僜僼僩僂僃傾傪僜乕僗僐乕僪偺宍偱棙梡偡傞応崌偵偼丆忋婰偺挊嶌
 *      尃昞帵丆偙偺棙梡忦審偍傛傃壓婰偺柍曐徹婯掕偑丆偦偺傑傑偺宍偱僜乕
 *      僗僐乕僪拞偵娷傑傟偰偄傞偙偲丏
 *  (2) 杮僜僼僩僂僃傾傪丆儔僀僽儔儕宍幃側偳丆懠偺僜僼僩僂僃傾奐敪偵巊
 *      梡偱偒傞宍偱嵞攝晍偡傞応崌偵偼丆嵞攝晍偵敽偆僪僉儏儊儞僩乮棙梡
 *      幰儅僯儏傾儖側偳乯偵丆忋婰偺挊嶌尃昞帵丆偙偺棙梡忦審偍傛傃壓婰
 *      偺柍曐徹婯掕傪宖嵹偡傞偙偲丏
 *  (3) 杮僜僼僩僂僃傾傪丆婡婍偵慻傒崬傓側偳丆懠偺僜僼僩僂僃傾奐敪偵巊
 *      梡偱偒側偄宍偱嵞攝晍偡傞応崌偵偼丆師偺偄偢傟偐偺忦審傪枮偨偡偙
 *      偲丏
 *    (a) 嵞攝晍偵敽偆僪僉儏儊儞僩乮棙梡幰儅僯儏傾儖側偳乯偵丆忋婰偺挊
 *        嶌尃昞帵丆偙偺棙梡忦審偍傛傃壓婰偺柍曐徹婯掕傪宖嵹偡傞偙偲丏
 *    (b) 嵞攝晍偺宍懺傪丆暿偵掕傔傞曽朄偵傛偭偰丆TOPPERS僾儘僕僃僋僩偵
 *        曬崘偡傞偙偲丏
 *  (4) 杮僜僼僩僂僃傾偺棙梡偵傛傝捈愙揑傑偨偼娫愙揑偵惗偠傞偄偐側傞懝
 *      奞偐傜傕丆忋婰挊嶌尃幰偍傛傃TOPPERS僾儘僕僃僋僩傪柶愑偡傞偙偲丏
 * 
 *  杮僜僼僩僂僃傾偼丆柍曐徹偱採嫙偝傟偰偄傞傕偺偱偁傞丏忋婰挊嶌尃幰偍
 *  傛傃TOPPERS僾儘僕僃僋僩偼丆杮僜僼僩僂僃傾偵娭偟偰丆偦偺揔梡壜擻惈傕
 *  娷傔偰丆偄偐側傞曐徹傕峴傢側偄丏傑偨丆杮僜僼僩僂僃傾偺棙梡偵傛傝捈
 *  愙揑傑偨偼娫愙揑偵惗偠偨偄偐側傞懝奞偵娭偟偰傕丆偦偺愑擟傪晧傢側偄丏
 * 
 */

#include "tl16pir552.h"
#include <s_services.h>
#include "sys_defs.h"	/* TNUM_PORT */

/*
 *	兪PD72001梡 娙堈SIO僪儔僀僶
 */

/* TNUM_PORT:僒億乕僩偡傞僔儕傾儖億乕僩悢 (僨僼僅儖僩抣 2), sys_defs.h 偵婰嵹 */

/*
 *  僔儕傾儖I/O億乕僩弶婜壔僽儘僢僋偺掕媊
 */
typedef struct sio_port_initialization_block {
	VP	channel_addr;	/* 僔儕傾儖億乕僩偺奐巒斣抧 */

	UB	lcr_def;	/* LCR愝掕抣 b0-b6;
				(憲庴怣價僢僩悢丄僗僩僢僾價僢僩丆僷儕僥傿) */
	UB	scr_def;	/* SCR愝掕抣乮僾儕僗働乕儔丟乯*/
	UB	boud_hi_def;	/* DLM愝掕抣乮儃乕儗乕僩忋埵偺愝掕抣乯 */
	UB	boud_lo_def;	/* DLL愝掕抣乮儃乕儗乕僩壓埵偺愝掕抣乯 */
} SIOPINIB;

/*
 *  僔儕傾儖I/O億乕僩娗棟僽儘僢僋偺掕媊
 */
struct sio_port_control_block {
	const SIOPINIB	*siopinib;	/* 僔儕傾儖I/O億乕僩弶婜壔僽儘僢僋 */
	VP_INT		exinf;		/* 奼挘忣曬 */
	BOOL		openflag;	/* 僆乕僾儞嵪傒僼儔僌 */
	UB		ier;		/* IER偺抣 */
	BOOL		getready;	/* 暥帤傪庴怣偟偨忬懺 */
	BOOL		putready;	/* 暥帤傪憲怣偱偒傞忬懺 */
};

/*
 *  僔儕傾儖I/O億乕僩弶婜壔僽儘僢僋
 *
 *  ID = 1 傪億乕僩1丆ID = 2 傪億乕僩2偵懳墳偝偣偰偄傞丏
 */
const SIOPINIB siopinib_table[TNUM_PORT] = {
	{ (VP)  UART_CH01,
	  (UB)	WORD_LENGTH_8 | STOP_BITS_1 | PARITY_NON,
	  (UB)	PRE_DIVISOR,
	  (UB)	HI8(DIVISOR),
	  (UB)	LO8(DIVISOR) },
#if TNUM_PORT >= 2
	{ (VP)  UART_CH02,
	  (UB)	WORD_LENGTH_8 | STOP_BITS_1 | PARITY_NON,
	  (UB)	PRE_DIVISOR,
	  (UB)	HI8(DIVISOR),
	  (UB)	LO8(DIVISOR) },
#endif /* TNUM_PORT >= 2 */
};

/*
 *  僔儕傾儖I/O億乕僩娗棟僽儘僢僋偺僄儕傾
 */
SIOPCB	siopcb_table[TNUM_PORT];

/*
 *  僔儕傾儖I/O億乕僩ID偐傜娗棟僽儘僢僋傪庢傝弌偡偨傔偺儅僋儘
 */
#define INDEX_SIOP(siopid)	((UINT)((siopid) - 1))
#define get_siopcb(siopid)	(&(siopcb_table[INDEX_SIOP(siopid)]))

/*
 *  忬懺偺撉弌偟乮IIR偺撉弌偟乯
 */
static void
tl16pir552_get_stat(SIOPCB *siopcb)
{
	UB	iir;

	iir = tl16pir552_read_reg( siopcb->siopinib->channel_addr, IIR) & INT_MASK;

	switch( iir ) {
		case INT_TRANS_EMPTY :
			siopcb->putready = TRUE;
			break;
		case INT_RECEIVE_DATA :
		case INT_CHAR_TIME_OUT :
			siopcb->getready = TRUE;
			break;
		default :
			break;
	}


}

/*
 *  暥帤傪庴怣偱偒傞偐丠
 */
Inline BOOL
tl16pir552_getready(SIOPCB *siopcb)
{
	return(siopcb->getready);
}

/*
 *  暥帤傪憲怣偱偒傞偐丠
 */
Inline BOOL
tl16pir552_putready(SIOPCB *siopcb)
{
	return(siopcb->putready);
}

/*
 *  庴怣偟偨暥帤偺庢弌偟
 */
Inline char
tl16pir552_getchar(SIOPCB *siopcb)
{
	siopcb->getready = FALSE;
	return((char) tl16pir552_read_reg( siopcb->siopinib->channel_addr, RBR ));
}

/*
 *  憲怣偡傞暥帤偺彂崬傒
 */
Inline void
tl16pir552_putchar(SIOPCB *siopcb, char c)
{
	siopcb->putready = FALSE;
	tl16pir552_write_reg( siopcb->siopinib->channel_addr, THR, c );
}

/*
 *  SIO僪儔僀僶偺弶婜壔儖乕僠儞
 */
void
tl16pir552_initialize()
{
	SIOPCB	*siopcb;
	UINT	i;

	/*
	 *  僔儖傾儖I/O億乕僩娗棟僽儘僢僋偺弶婜壔
	 */
	for (siopcb = siopcb_table, i = 0; i < TNUM_PORT; siopcb++, i++) {
		siopcb->siopinib = &(siopinib_table[i]);
		siopcb->openflag = FALSE;
	}
}

/*
 *  僆乕僾儞偟偰偄傞億乕僩偑偁傞偐丠
 */
BOOL
tl16pir552_openflag(void)
{
#if TNUM_PORT < 2
	return(siopcb_table[0].openflag);
#else /* TNUM_PORT < 2 */
	return(siopcb_table[0].openflag || siopcb_table[1].openflag);
#endif /* TNUM_PORT < 2 */
}

/*
 *  僔儕傾儖I/O億乕僩偺僆乕僾儞
 */
SIOPCB *
tl16pir552_opn_por(ID siopid, VP_INT exinf)
{
	SIOPCB		*siopcb;
	const SIOPINIB	*siopinib;
	VP	 scc_base_addr;

	siopcb = get_siopcb(siopid);
	siopinib = siopcb->siopinib;

	/* 僔儕傾儖僐儞僩儘乕儔偺弶婜壔 */
	scc_base_addr = siopinib->channel_addr;

	tl16pir552_write_reg( scc_base_addr, IER,	DIS_INT );

	tl16pir552_write_reg( scc_base_addr, MCR,	ENABLE_EXT_INT );

	tl16pir552_write_reg( scc_base_addr, LCR,	siopinib->lcr_def | DIVISOR_LATCH_ACC );

	tl16pir552_write_reg( scc_base_addr, SCR,	siopinib->scr_def );

	tl16pir552_write_reg( scc_base_addr, DLL,	siopinib->boud_lo_def );
	tl16pir552_write_reg( scc_base_addr, DLM,	siopinib->boud_hi_def );

	tl16pir552_write_reg( scc_base_addr, LCR,	siopinib->lcr_def );

	tl16pir552_write_reg( scc_base_addr, FCR,	FIFO_ENABLE );
	tl16pir552_write_reg( scc_base_addr, FCR,	FIFO_ENABLE | RECEIVE_FIFO_RESET | TRANS_FIFO_RESET | RECEIVE_TRIG_1_BYTE);
	tl16pir552_write_reg( scc_base_addr, FCR,	FIFO_ENABLE | RECEIVE_TRIG_1_BYTE );

	tl16pir552_write_reg( scc_base_addr, MCR,	DTR | RTS | ENABLE_EXT_INT );

	tl16pir552_write_reg( scc_base_addr, IER,	RECEIVE_DATA_AVAILABLE);

	/* 妱崬傒儗儀儖愝掕丄妱崬傒梫媮僋儕傾偼丄sio_opn_por(hw_serial.h)偱峴偆丅 */

	siopcb->exinf = exinf;
	siopcb->getready = siopcb->putready = FALSE;
	siopcb->openflag = TRUE;

	return(siopcb);
}

/*
 *  僔儕傾儖I/O億乕僩偺僋儘乕僘
 */
void
tl16pir552_cls_por(SIOPCB *siopcb)
{
	tl16pir552_write_reg( siopcb->siopinib->channel_addr, IER, DIS_INT );

	siopcb->openflag = FALSE;
}

/*
 *  僔儕傾儖I/O億乕僩傊偺暥帤憲怣
 */
BOOL
tl16pir552_snd_chr(SIOPCB *siopcb, char c)
{
	if (tl16pir552_putready(siopcb)) {
		tl16pir552_putchar(siopcb, c);
		return(TRUE);
	}
	return(FALSE);
}

/*
 *  僔儕傾儖I/O億乕僩偐傜偺暥帤庴怣
 */
INT
tl16pir552_rcv_chr(SIOPCB *siopcb)
{
	if (tl16pir552_getready(siopcb)) {
		return((INT)(UB) tl16pir552_getchar(siopcb));
	}
	return(-1);
}

/*
 *  僔儕傾儖I/O億乕僩偐傜偺僐乕儖僶僢僋偺嫋壜
 */
void
tl16pir552_ena_cbr(SIOPCB *siopcb, UINT cbrtn)
{
	UB	temp;
	UB	ier_bit = 0;

	switch (cbrtn) {
	case SIO_ERDY_SND:
		ier_bit = TRANS_REG_EMPTY;
		break;
	case SIO_ERDY_RCV:
		ier_bit = RECEIVE_DATA_AVAILABLE | RECEIVE_LINE_STATUS;
		break;
	}

	temp = tl16pir552_read_reg( siopcb->siopinib->channel_addr, IER );
	temp |= ier_bit;
	siopcb->ier = temp;
	tl16pir552_write_reg( siopcb->siopinib->channel_addr, IER, temp );
}

/*
 *  僔儕傾儖I/O億乕僩偐傜偺僐乕儖僶僢僋偺嬛巭
 */
void
tl16pir552_dis_cbr(SIOPCB *siopcb, UINT cbrtn)
{
	UB	temp;
	UB	ier_bit = 0;

	switch (cbrtn) {
	case SIO_ERDY_SND:
		ier_bit = TRANS_REG_EMPTY;
		break;
	case SIO_ERDY_RCV:
		ier_bit = RECEIVE_DATA_AVAILABLE | RECEIVE_LINE_STATUS;
		break;
	}

	temp = tl16pir552_read_reg( siopcb->siopinib->channel_addr, IER );
	temp &= ~ier_bit;
	siopcb->ier = temp;
	tl16pir552_write_reg( siopcb->siopinib->channel_addr, IER, temp );
}

/*
 *  僔儕傾儖I/O億乕僩偵懳偡傞妱崬傒張棟
 */
static void
tl16pir552_isr_siop(SIOPCB *siopcb)
{
	tl16pir552_get_stat(siopcb);

	if ( tl16pir552_getready(siopcb) ) {
		/*
		 *  庴怣捠抦僐乕儖僶僢僋儖乕僠儞傪屇傃弌偡丏
		 */
		tl16pir552_ierdy_rcv(siopcb->exinf);
	} else if ( tl16pir552_putready(siopcb) ) {
		/*
		 *  憲怣壜擻僐乕儖僶僢僋儖乕僠儞傪屇傃弌偡丏
		 */
		tl16pir552_ierdy_snd(siopcb->exinf);
	}
}

/*
 *  SIO偺妱崬傒僒乕價僗儖乕僠儞
 */
void
tl16pir552_uart0_isr()
{
	if (siopcb_table[0].openflag) {
		tl16pir552_isr_siop(&(siopcb_table[0]));
	}
}

#if TNUM_PORT >= 2
void
tl16pir552_uart1_isr()
{
	if (siopcb_table[1].openflag) {
		tl16pir552_isr_siop(&(siopcb_table[1]));
	}
}
#endif /* TNUM_SIOP >= 2 */