tl16pir552.h

JAPAN RTOS TOPPERS/JSP kernel 1.4 PreRelease simulation environment JSP kernel Windows simulation

/*
 *  TOPPERS/JSP Kernel
 *      Toyohashi Open Platform for Embedded Real-Time Systems/
 *      Just Standard Profile Kernel
 * 
 *  Copyright (C) 2000-2003 by Embedded and Real-Time Systems Laboratory
 *                              Toyohashi Univ. of Technology, JAPAN
 * 
 *  忋婰挊嶌尃幰偼丆埲壓偺 (1)乣(4) 偺忦審偐丆Free Software Foundation 
 *  偵傛偭偰岞昞偝傟偰偄傞 GNU General Public License 偺 Version 2 偵婰
 *  弎偝傟偰偄傞忦審傪枮偨偡応崌偵尷傝丆杮僜僼僩僂僃傾乮杮僜僼僩僂僃傾
 *  傪夵曄偟偨傕偺傪娷傓丏埲壓摨偠乯傪巊梡丒暋惢丒夵曄丒嵞攝晍乮埲壓丆
 *  棙梡偲屇傇乯偡傞偙偲傪柍彏偱嫋戻偡傞丏
 *  (1) 杮僜僼僩僂僃傾傪僜乕僗僐乕僪偺宍偱棙梡偡傞応崌偵偼丆忋婰偺挊嶌
 *      尃昞帵丆偙偺棙梡忦審偍傛傃壓婰偺柍曐徹婯掕偑丆偦偺傑傑偺宍偱僜乕
 *      僗僐乕僪拞偵娷傑傟偰偄傞偙偲丏
 *  (2) 杮僜僼僩僂僃傾傪丆儔僀僽儔儕宍幃側偳丆懠偺僜僼僩僂僃傾奐敪偵巊
 *      梡偱偒傞宍偱嵞攝晍偡傞応崌偵偼丆嵞攝晍偵敽偆僪僉儏儊儞僩乮棙梡
 *      幰儅僯儏傾儖側偳乯偵丆忋婰偺挊嶌尃昞帵丆偙偺棙梡忦審偍傛傃壓婰
 *      偺柍曐徹婯掕傪宖嵹偡傞偙偲丏
 *  (3) 杮僜僼僩僂僃傾傪丆婡婍偵慻傒崬傓側偳丆懠偺僜僼僩僂僃傾奐敪偵巊
 *      梡偱偒側偄宍偱嵞攝晍偡傞応崌偵偼丆師偺偄偢傟偐偺忦審傪枮偨偡偙
 *      偲丏
 *    (a) 嵞攝晍偵敽偆僪僉儏儊儞僩乮棙梡幰儅僯儏傾儖側偳乯偵丆忋婰偺挊
 *        嶌尃昞帵丆偙偺棙梡忦審偍傛傃壓婰偺柍曐徹婯掕傪宖嵹偡傞偙偲丏
 *    (b) 嵞攝晍偺宍懺傪丆暿偵掕傔傞曽朄偵傛偭偰丆TOPPERS僾儘僕僃僋僩偵
 *        曬崘偡傞偙偲丏
 *  (4) 杮僜僼僩僂僃傾偺棙梡偵傛傝捈愙揑傑偨偼娫愙揑偵惗偠傞偄偐側傞懝
 *      奞偐傜傕丆忋婰挊嶌尃幰偍傛傃TOPPERS僾儘僕僃僋僩傪柶愑偡傞偙偲丏
 * 
 *  杮僜僼僩僂僃傾偼丆柍曐徹偱採嫙偝傟偰偄傞傕偺偱偁傞丏忋婰挊嶌尃幰偍
 *  傛傃TOPPERS僾儘僕僃僋僩偼丆杮僜僼僩僂僃傾偵娭偟偰丆偦偺揔梡壜擻惈傕
 *  娷傔偰丆偄偐側傞曐徹傕峴傢側偄丏傑偨丆杮僜僼僩僂僃傾偺棙梡偵傛傝捈
 *  愙揑傑偨偼娫愙揑偵惗偠偨偄偐側傞懝奞偵娭偟偰傕丆偦偺愑擟傪晧傢側偄丏
 * 
 */

#ifndef _TL16PIR552_H_
#define _TL16PIR552_H_

#include <t_config.h>

/*
 *  僔儕傾儖乛僷儔儗儖 I/O TL16PIR552(TI) 娭楢偺掕媊
 */
/* TL16PIR552偺儗僕僗僞偺傾僪儗僗 */
#define RBR	0x00	/* Receiver Buffer (撉傒弌偟) */
#define THR	0x00	/* Transmitter Holding Register (彂偒弌偟) */
#define DLL	0x00	/* Divisor Latch (LSB) */
#define IER	0x10	/* Interrupt-Enable Register */
#define DLM	0x10	/* Divisor Latch (MSB) */
#define	IIR	0x20	/* Interrupt-Ident Register (撉傒弌偟) */
#define	FCR	0x20	/* FIFO Control Register (彂偒弌偟) */
#define	LCR	0x30	/* Line-Control Register */
#define	MCR	0x40	/* Modem-Control Register */
#define	LSR	0x50	/* Line-Status Register */
#define	MSR	0x60	/* Modem-Status Register */
#define	SCR	0x70	/* Scratch Register */

/* for LCR */
#define	WORD_LENGTH_8		BIT1 | BIT0
#define	STOP_BITS_1		0		/* BIT2 */
#define	PARITY_NON		0		/* BIT3, 4 */
/* BIT5,6 徣棯 */
#define	DIVISOR_LATCH_ACC	BIT7

/* for IER */
#define	DIS_INT			0
#define	RECEIVE_DATA_AVAILABLE	BIT0
#define	TRANS_REG_EMPTY		BIT1
#define RECEIVE_LINE_STATUS	BIT2
#define MODEM_STATUS		BIT3

/* for MCR */
#define	DTR			BIT0
#define	RTS			BIT1
#define	ENABLE_EXT_INT		BIT3
#define	AUTOFLOW_CONTROL	BIT5

/* for FCR */
#define	FIFO_ENABLE		BIT0
#define	RECEIVE_FIFO_RESET	BIT1
#define	TRANS_FIFO_RESET	BIT2
#define RECEIVE_TRIG_1_BYTE	0	/* BIT6, 7 */
#define RECEIVE_TRIG_4_BYTE	BIT6
#define	RECEIVE_TRIG_8_BYTE	BIT7
#define	RECEIVE_TRIG_14_BYTE	BIT6 | BIT7

/* for IIR */
#define	INT_MASK		0x0f
#define	INT_RECEIVE_DATA	BIT2
#define INT_CHAR_TIME_OUT	BIT3 | BIT2
#define	INT_TRANS_EMPTY		BIT1

/* 儃乕儗乕僩掕媊娭學 */
#define	PRE_DIVISOR	4
#define	DIVISOR		XIN_CLOCK / (8 * DEVIDE_RATIO * PRE_DIVISOR)

/*
 *  僔儕傾儖I/O億乕僩娗棟僽儘僢僋偺掕媊
 */
typedef struct sio_port_control_block	SIOPCB;

/*
 *  僐乕儖僶僢僋儖乕僠儞偺幆暿斣崋
 */
#define SIO_ERDY_SND	1u		/* 憲怣壜擻僐乕儖僶僢僋 */
#define SIO_ERDY_RCV	2u		/* 庴怣捠抦僐乕儖僶僢僋 */

/*
 *  SIO僪儔僀僶偺弶婜壔儖乕僠儞
 */
extern void	tl16pir552_initialize(void);

/*
 *  僆乕僾儞偟偰偄傞億乕僩偑偁傞偐丠
 */
extern BOOL	tl16pir552_openflag(void);

/*
 *  僔儕傾儖I/O億乕僩偺僆乕僾儞
 */
extern SIOPCB	*tl16pir552_opn_por(ID siopid, VP_INT exinf);

/*
 *  僔儕傾儖I/O億乕僩偺僋儘乕僘
 */
extern void	tl16pir552_cls_por(SIOPCB *siopcb);

/*
 *  僔儕傾儖I/O億乕僩傊偺暥帤憲怣
 */
extern BOOL	tl16pir552_snd_chr(SIOPCB *siopcb, char c);

/*
 *  僔儕傾儖I/O億乕僩偐傜偺暥帤庴怣
 */
extern INT	tl16pir552_rcv_chr(SIOPCB *siopcb);

/*
 *  僔儕傾儖I/O億乕僩偐傜偺僐乕儖僶僢僋偺嫋壜
 */
extern void	tl16pir552_ena_cbr(SIOPCB *siopcb, UINT cbrtn);

/*
 *  僔儕傾儖I/O億乕僩偐傜偺僐乕儖僶僢僋偺嬛巭
 */
extern void	tl16pir552_dis_cbr(SIOPCB *siopcb, UINT cbrtn);

/*
 *  SIO偺妱崬傒僒乕價僗儖乕僠儞
 */
extern void	tl16pir552_uart0_isr(void);
extern void	tl16pir552_uart1_isr(void);

/*
 *  僔儕傾儖I/O億乕僩偐傜偺憲怣壜擻僐乕儖僶僢僋
 */
extern void	tl16pir552_ierdy_snd(VP_INT exinf);

/*
 *  僔儕傾儖I/O億乕僩偐傜偺庴怣捠抦僐乕儖僶僢僋
 */
extern void	tl16pir552_ierdy_rcv(VP_INT exinf);

/*============================================================================*/
/* 埲壓偼丄杮摉偼ti16pir552_sil.h偲偄偆僼傽僀儖偵擖傞傋偒偩偲巚偆丅 */

/*
 *  僨僶僀僗儗僕僗僞偺傾僋僙僗娫妘帪娫乮nsec扨埵乯
 */
#define	tl16pir552_DELAY	100u	/* 抣偵崻嫆偼側偄 */
/* 僶僫乕岦偗 */
#define	tl16pir552_DELAY_POR	1100000u	/* 暥帤傪棊偲偝側偄掱搙偵愝掕 */

/*
 *  僨僶僀僗儗僕僗僞傊偺傾僋僙僗娭悢
 */
Inline UB tl16pir552_read_reg( VP addr, UB reg ) {

	UB	val;

	val = (UB) sil_reb_mem( (VP) (addr + reg) );
	sil_dly_nse( tl16pir552_DELAY );

	return(val);
}

Inline void tl16pir552_write_reg(VP addr, UB reg, UB val) {

	sil_wrb_mem( (VP) (addr + reg), (VB) val );
	sil_dly_nse( tl16pir552_DELAY );
}

/* sys_putc(c)岦偗 */
Inline void tl16pir552_write_por(VP addr, UB reg, UB val) {

	sil_wrb_mem( (VP) (addr + reg), (VB) val );
	sil_dly_nse( tl16pir552_DELAY_POR );
}

/*============================================================================*/
/* sys_config.c岦偗僔儕傾儖僐儞僩儘乕儔偺弶婜壔 */
#define scc_init( addr )						\
	tl16pir552_write_reg( addr, IER, DIS_INT );			\
	tl16pir552_write_reg( addr, LCR, WORD_LENGTH_8 | STOP_BITS_1 | PARITY_NON | DIVISOR_LATCH_ACC ); \
	tl16pir552_write_reg( addr, SCR, PRE_DIVISOR );			\
	tl16pir552_write_reg( addr, DLL, LO8(DIVISOR) );		\
	tl16pir552_write_reg( addr, DLM, HI8(DIVISOR) );		\
	tl16pir552_write_reg( addr, LCR, WORD_LENGTH_8 | STOP_BITS_1 | PARITY_NON ); \
	tl16pir552_write_reg( addr, IER, RECEIVE_DATA_AVAILABLE)

#endif /* _TL16PIR552_H_ */