w83977.h

本程序在S3C44B0 uClinux的嵌入式GUI

/******************************************************************************
The Registers define for W83977
******************************************************************************/

#ifndef __W83977_H__
#define __W83977_H__

//*****************************************************************************

//w83977 config
//w83977 CS ----------- nGCS4
//Address is From 0x8000000 to 0x9ffffff
#define W83977_BaseAddr		(0x8000000)

#define HEFRAS	0

#if(!(HEFRAS))
	#define Extend_Index_Reg  (*(volatile unsigned char *)(W83977_BaseAddr+0x3f0))
	#define Extend_Date_Reg   (*(volatile unsigned char *)(W83977_BaseAddr+0x3f1))
#else
	#define Extend_Index_Reg  (*(volatile unsigned char *)(W83977_BaseAddr+0x370))
	#define Extend_Date_Reg   (*(volatile unsigned char *)(W83977_BaseAddr+0x371))
#endif

//**************************************************************************

#define W83977_CR02		0x02
	//Bit 0 : soft Reset
#define W83977_CR07		0x07
	//Bit 7 - 0: LDNB7 - LDNB0 --> Logical Device Number Bit 7 - 0
#define W83977_CR20		0x20
	//Bit 7 - 0: DEVIDB7 - DEBIDB0 --> Device ID Bit 7 - Bit 0 = 0x52 (read only)
#define W83977_CR21		0x21
	//Bit 7 - 0: DEVREVB7 - DEBREVB0 --> Device Rev Bit 7 - Bit 0 = 0xFx (read only)
#define W83977_CR22		0x22
/*	Bit 5: URBPWD
		= 0 Power down
		= 1 No Power down
	Bit 4: URAPWD
		= 0 Power down
		= 1 No Power down
	Bit 3: PRTPWD
		= 0 Power down
		= 1 No Power down
	Bit 2, 1: Reserved.
	Bit 0: FDCPWD
		= 0 Power down
		= 1 No Power down	*/
	#define URBPWD		1
	#define URAPWD		1
	#define PRTPWD		1
	#define FDCPWD		1
#define W83977_CR23		0x23
	//Bit 0: IPD (Immediate Power Down). When set to 1, it will 
	//put the whole chip into power down mode immediately.
#define W83977_CR24		0x24
	/*Bit 7: EN16SA
		= 0 12 bit Address Qualification
		= 1 16 bit Address Qualification
	Bit 6: EN48
		= 0 The clock input on Pin 1 should be 24 Mhz.
		= 1 The clock input on Pin 1 should be 48 Mhz.
	The corresponding power-on setting pin is SOUTB (pin 53).
	Bit 5 - 3: Reserved.
	Bit 2: ENKBC
		= 0 KBC is disabled after hardware reset.
		= 1 KBC is enabled after hardware reset.
	This bit is read only, and set/reset by power-on setting pin. The corresponding power-on
	setting pin is SOUTA (pin 46).
	Bit 1: Reserved
	Bit 0: PNPCSV#
		= 0 The Compatible PnP address select registers have default values.
		= 1 The Compatible PnP address select registers have no default value.
	When trying to make a change to this bit, new value of PNPCSV# must be complementary to
	the old one to make an effective change. For example, the user must set PNPCSV# to 0 first
	and then reset it to 1 to reset these PnP registers if the present value of PNPCSV# is 1. The
	corresponding power-on setting pin is NDTRA (pin 44).*/
#define W83977_CR25		0x25
	/*Bit 5: URBTRI
	Bit 4: URATRI
	Bit 3: PRTTRI
	Bit 2 - 1 : Reserved
	Bit 0: FDCTRI.*/
#define W83977_CR26		0x26
	/*Bit 7: SEL4FDD
		= 0 Select two FDD mode.
		= 1 Select four FDD mode.
	Bit 6: HEFRAS
	These two bits define how to enable Configuration mode. The corresponding power-on
	setting pin is NRTSA (pin 43).
	HEFRAS Address and Value
		= 0 Write 87h to the location 3F0h twice.
		= 1 Write 87h to the location 370h twice.
	Bit 5: LOCKREG
		= 0 Enable R/W Configuration Registers.
		= 1 Disable R/W Configuration Registers.
	Bit 4: Reserved.
	Bit 3: DSFDLGRQ
		= 0 Enable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is effective
		on selecting IRQ
		= 1 Disable FDC legacy mode on IRQ and DRQ selection, then DO register bit 3 is not
		effective on selecting IRQ
	Bit 2: DSPRLGRQ
		= 0 Enable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is effective on
		selecting IRQ
		= 1 Disable PRT legacy mode on IRQ and DRQ selection, then DCR bit 4 is not effective
		on selecting IRQ
	Bit 1: DSUALGRQ
		= 0 Enable UART A legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
		IRQ
		= 1 Disable UART A legacy mode IRQ selecting, then MCR bit 3 is not effective on
		selecting IRQ
	Bit 0: DSUBLGRQ
		= 0 Enable UART B legacy mode IRQ selecting, then MCR bit 3 is effective on selecting
		IRQ
		= 1 Disable UART B legacy mode IRQ selecting, then MCR bit 3 is not effective on
		selecting IRQ*/
#define W83977_CR28		0x28
	/*Bit 4: IRQ Sharing selection.
		= 0 Disable IRQ Sharing
		= 1 Enable IRQ Sharing
	Bit 3:Reserved
	Bit 2 - 0: PRTMODS2 - PRTMODS0
		= 0xx Parallel Port Mode
		= 100 Reserved
		= 101 External FDC Mode
		= 110 Reserved
		= 111 External two FDC Mode*/
#define W83977_CR2a		0x2a
	/*Bit 7: PIN57S
		= 0 KBRST
		= 1 GP12
	Bit 6: PIN56S
		= 0 GA20
		= 1 GP11
	Bit 5 - 4: PIN40S1, PIN40S0
		= 00 CIRRX
		= 01 GP24
		= 10 8042 P13
		= 11 Reserved
	Bit 3 - 2: PIN39S1, PIN39S0
		= 00 SUSCIN#
		= 01 Reserved
		= 10 GP25
		= 11 Reserved
	Bit 1 - 0: PIN3S1, PIN3S0
		= 00 DRVDEN1
		= 01 GP10
		= 10 8042 P12
		= 11 SCI#*/
#define W83977_CR2b		0x2b
	/*Bit 7 - 6: PIN73S1, PIN73S0
		= 00 PANSWIN#
		= 01 GP23
		= 10 Reserved
		= 11 Reserved
	Bit 5: PIN72S
		= 0 PANSWOUT#
		= 1 GP22
	Bit 4 - 3: PIN70S1, PIN70S0
		= 00 SMI#
		= 01 GP21
		= 10 8042 P16
		= 11 Reserved
	Bit 2 - 1: PIN69S1, PIN69S0
		= 00 PWRCTL#
		= 01 GP20
		= 10 Reserved
		= 11 Reserved
	Bit 0: PIN58S
		= 0 KBLOCK
		= 1 GP13*/
#define W83977_CR2c		0x2c
	/*Bit 7 - 6: PIN121S1, PIN121S0
		= 00 DRQ0
		= 01 GP17
		= 10 8042 P14
		= 11 SCI#
	Bit 5 - 4: PIN119S1, PIN119S0
		= 00 NDACK0
		= 01 GP16
		= 10 8042 P15
		= 11 Reserved
	Bit 3 - 2: PIN104S1, PIN104S0
		= 00 IRQ15
		= 01 GP15
		= 10 WDTO
		= 11 Reserved
	Bit 1 - 0: PIN103S1, PIN103S0
		= 00 IRQ14
		= 01 GP14
		= 10 PLEDO
		= 11 Reserved*/
#define W83977_CR2d		0x2d
/*Test Modes: Reserved for Winbond.*/
#define W83977_CR2e		0x2e
/*Test Modes: Reserved for Winbond.*/
#define W83977_CR2f		0x2f
/*Test Modes: Reserved for Winbond.*/

//*****************************************************************************

//Next is For Logical Device 1 ( Parallel Port )
#define PPT_CR30		0x30
	/*Bit 0:
		= 1 Activates the logical device.
		= 0 Logical device is inactive.*/
#define PPT_CR60		0x60
#define PPT_CR61		0x61
	/*These two registers select Parallel Port I/O base address.
	[0x100:0xFFC] on 4 byte boundary (EPP not supported) or
	[0x100:0xFF8] on 8 byte boundary (all modes supported,
	EPP is only available when the base
	address is on 8 byte boundary).*/
#define PPT_CR70		0x70
	/*Bit [3:0]: These bits select IRQ resource for Parallel Port.*/
#define PPT_CR74		0x74
	/*Bit 2 - 0: These bits select DRQ resource for Parallel Port.
		0x00=DMA0
		0x01=DMA1
		0x02=DMA2
		0x03=DMA3
		0x04 - 0x07= No DMA active*/
#define PPT_CRf0		0xf0
	/*Bit 7: PP Interrupt Type:
	Not valid when the parallel port is in the printer Mode (100) or the standard & Bi-directional
	Mode (000).
		= 1 Pulsed Low, released to high-Z .
		= 0 IRQ follows nACK when parallel port in EPP Mode or [Printer, SPP, EPP] under ECP.
	Bit [6:3]: ECP FIFO Threshold.
	Bit 2 - 0 Parallel Port Mode
		= 100 Printer Mode (Default)
		= 000 Standard and Bi-direction (SPP) mode
		= 001 EPP - 1.9 and SPP mode
		= 101 EPP - 1.7 and SPP mode
		= 010 ECP mode
		= 011 ECP and EPP - 1.9 mode
		= 111 ECP and EPP - 1.7 mode.*/

//*****************************************************************************

//Next is For Logical Device 2 ( UARTA )
#define UARTA_CR30		0x30
	/*Bit 0:
		= 1 Activates the logical device.
		= 0 Logical device is inactive.*/
#define UARTA_CR60		0x60
#define UARTA_CR61		0x61
	//These two registers select Serial Port 1 I/O 
	//base address [0x100:0xFF8] on 8 byte boundary.
#define UARTA_CR70		0x70
	/*Bit 3 - 0: These bits select IRQ resource for Serial Port 1.*/
#define UARTA_CRf0		0xf0
	/*Bit 1 - 0: SUACLKB1, SUACLKB0
		= 00 UART A clock source is 1.8462 Mhz (24MHz/13)
		= 01 UART A clock source is 2 Mhz (24MHz/12)
		= 10 UART A clock source is 24 Mhz (24MHz/1)
		= 11 UART A clock source is 14.769 Mhz (24MHz/1.625)*/

//*****************************************************************************

//Next is For Logical Device 3 ( UARTB )
#define UARTB_CR30		0x30
	/*Bit 0:
		= 1 Activates the logical device.
		= 0 Logical device is inactive.*/
#define UARTB_CR60		0x60
#define UARTB_CR61		0x61
	//These two registers select Serial Port 2 I/O 
	//base address [0x100:0xFF8] on 8 byte boundary.
#define UARTB_CR70		0x70
	/*Bit 3 - 0: These bits select IRQ resource for Serial Port 2 */
#define UARTB_CRf0		0xf0
#define UARTB_CRf1		0xf1

//*****************************************************************************

//Next is For Logical Device 5 ( KBC )
#define KBC_CR30		0x30
	/*Bit 0:
		= 1 Activates the logical device.
		= 0 Logical device is inactive.*/
#define KBC_CR60		0x60
#define KBC_CR61		0x61
	//These two registers select the first KBC I/O 
	//base address [0x100:0xFFF] on 1 byte boundary.
#define KBC_CR62		0x62
#define KBC_CR63		0x63
	//These two registers select the second KBC I/O
	//base address [0x100:0xFFF] on 1 byte boundary.
#define KBC_CR70		0x70
	//Bit [3:0]: These bits select IRQ resource for KINT (keyboard).
#define KBC_CR72		0x72
	//Bit [3:0]: These bits select IRQ resource for MINT (PS2 Mouse)
#define KBC_CRf0		0xf0
	/*Bit 7 - 6: KBC clock rate selection
		= 00 Select 6MHz as KBC clock input.
		= 01 Select 8MHz as KBC clock input.
		= 10 Select 12Mhz as KBC clock input.
		= 11 Select 16Mhz as KBC clock input.
	Bit 5 - 3: Reserved.
	Bit 2: = 0 Port 92 disable.
		= 1 Port 92 enable.
	Bit 1: = 0 Gate20 software control.
		= 1 Gate20 hardware speed up.
	Bit 0: = 0 KBRST software control.
		= 1 KBRST hardware speed up.*/

//*****************************************************************************

#define PPT_BaseL		0x78
#define PPT_BaseH		0x03
#define PPT_BaseAddr		( W83977_BaseAddr+((PPT_BaseH<<8)|PPT_BaseL) )

//EPP mode
#define PPT_PORT		(*(volatile unsigned char *)(PPT_BaseAddr+0x000))
#define PPT_STATUS		(*(volatile unsigned char *)(PPT_BaseAddr+0x001))
#define PPT_LATCH		(*(volatile unsigned char *)(PPT_BaseAddr+0x002))
#define PPT_SWAP		(*(volatile unsigned char *)(PPT_BaseAddr+0x002))
#define PPT_ADDR		(*(volatile unsigned char *)(PPT_BaseAddr+0x003))
#define PPT_DATA_0		(*(volatile unsigned char *)(PPT_BaseAddr+0x004))
#define PPT_DATA_1		(*(volatile unsigned char *)(PPT_BaseAddr+0x005))
#define PPT_DATA_2		(*(volatile unsigned char *)(PPT_BaseAddr+0x006))
#define PPT_DATA_3		(*(volatile unsigned char *)(PPT_BaseAddr+0x007))

//ECP mode
#define PPT_data		(*(volatile unsigned char *)(PPT_BaseAddr+0x000))
#define PPT_ecpAFifo	(*(volatile unsigned char *)(PPT_BaseAddr+0x000))
#define PPT_dsr			(*(volatile unsigned char *)(PPT_BaseAddr+0x001))
#define PPT_dcr			(*(volatile unsigned char *)(PPT_BaseAddr+0x002))
#define PPT_cFifo		(*(volatile unsigned char *)(PPT_BaseAddr+0x400))
#define PPT_ecpDFifo	(*(volatile unsigned char *)(PPT_BaseAddr+0x400))
#define PPT_tFifo		(*(volatile unsigned char *)(PPT_BaseAddr+0x400))
#define PPT_cnfgA		(*(volatile unsigned char *)(PPT_BaseAddr+0x400))
#define PPT_cnfgB		(*(volatile unsigned char *)(PPT_BaseAddr+0x401))
#define PPT_ecr			(*(volatile unsigned char *)(PPT_BaseAddr+0x401))

//*****************************************************************************

#define UARTA_BaseL		0xf8
#define UARTA_BaseH		0x03
#define UARTA_BaseAddr		( W83977_BaseAddr+((UARTA_BaseH<<8)|UARTA_BaseL) )

#define UARTA_RBR		(*(volatile unsigned char *)(UARTA_BaseAddr+0))
#define UARTA_TBR		(*(volatile unsigned char *)(UARTA_BaseAddr+0))
#define UARTA_ICR		(*(volatile unsigned char *)(UARTA_BaseAddr+1))
#define UARTA_ISR		(*(volatile unsigned char *)(UARTA_BaseAddr+2))
#define UARTA_UFR		(*(volatile unsigned char *)(UARTA_BaseAddr+2))
#define UARTA_UCR		(*(volatile unsigned char *)(UARTA_BaseAddr+3))
#define UARTA_HCR		(*(volatile unsigned char *)(UARTA_BaseAddr+4))
#define UARTA_USR		(*(volatile unsigned char *)(UARTA_BaseAddr+5))
#define UARTA_HSR		(*(volatile unsigned char *)(UARTA_BaseAddr+6))
#define UARTA_UDR		(*(volatile unsigned char *)(UARTA_BaseAddr+7))
#define UARTA_BLL		(*(volatile unsigned char *)(UARTA_BaseAddr+0))
#define UARTA_BHL		(*(volatile unsigned char *)(UARTA_BaseAddr+1))

//*****************************************************************************

#define UARTB_BaseL		0xf8
#define UARTB_BaseH		0x02
#define UARTB_BaseAddr		( W83977_BaseAddr+((UARTB_BaseH<<8)|UARTB_BaseL) )

#define UARTB_RBR		(*(volatile unsigned char *)(UARTB_BaseAddr+0))
#define UARTB_TBR		(*(volatile unsigned char *)(UARTB_BaseAddr+0))
#define UARTB_ICR		(*(volatile unsigned char *)(UARTB_BaseAddr+1))
#define UARTB_ISR		(*(volatile unsigned char *)(UARTB_BaseAddr+2))
#define UARTB_UFR		(*(volatile unsigned char *)(UARTB_BaseAddr+2))
#define UARTB_UCR		(*(volatile unsigned char *)(UARTB_BaseAddr+3))
#define UARTB_HCR		(*(volatile unsigned char *)(UARTB_BaseAddr+4))
#define UARTB_USR		(*(volatile unsigned char *)(UARTB_BaseAddr+5))
#define UARTB_HSR		(*(volatile unsigned char *)(UARTB_BaseAddr+6))
#define UARTB_UDR		(*(volatile unsigned char *)(UARTB_BaseAddr+7))
#define UARTB_BLL		(*(volatile unsigned char *)(UARTB_BaseAddr+0))
#define UARTB_BHL		(*(volatile unsigned char *)(UARTB_BaseAddr+1))

//*****************************************************************************

#define KBC_BaseL_1		0x60
#define KBC_BaseH_1		0x00
#define KBC_BaseL_2		0x64
#define KBC_BaseH_2		0x00
#define KBC_BaseAddr_1		( W83977_BaseAddr+((KBC_BaseH_1<<8)|KBC_BaseL_1) )
#define KBC_BaseAddr_2		( W83977_BaseAddr+((KBC_BaseH_2<<8)|KBC_BaseL_2) )

#define KBC_INBUF		(*(volatile unsigned char *)KBC_BaseAddr_2)
#define KBC_OUTBUF		(*(volatile unsigned char *)KBC_BaseAddr_1)

//*****************************************************************************

#define UART_Channel_A		0
#define UART_Channel_B		1
#define UART_Channel_C		2
#define UART_Channel_D		3

#define ON		1
#define OFF		0

//*****************************************************************************
void Ext_Funct_Reg_W( unsigned char addr, unsigned char data );
unsigned char Ext_Funct_Reg_R( unsigned char addr );

void W83977_KBC_Init(void) ;
void W83977_KBC_Test(void) ;
void W83977_UartA_Init(void) ;
void W83977_UartB_Init(void) ;
void W83977_UartA_Test(void) ;
void W83977_UartB_Test(void) ;
void W83977_PPT_Test(void) ;

//*****************************************************************************

#endif  /*__W83977_H___*/