mcf5202_lo.s

motorola自己开发的针对coldfire 5272的Dbug bootloader程序

/*
 * File:	mcf5202_lo.s
 * Purpose:	Lowest level routines for MCF5202.
 *
 * Notes:	This file assembles with both Diab and GNU tools
 *
 * Author:	Eric DeVolder
 * Date:
 *
 * Modifications:
 *
 */

	/*
	 * This file contains the low level assembly routines to do
	 * things that C can not.  It also contains the two initial
	 * vectors needed for ROM boot-up.
	 */

#ifdef _UNDERSCORE_
#define main _main
#endif

	.extern VECTOR_TABLE
	.extern main
	.extern ___SP_INIT

	.global asm_startmeup
	.global cpu_cache_flush

	.global _asm_startmeup
	.global _cpu_cache_flush

	.text

/*
 * Main entry point upon reset.
 */
asm_startmeup:
_asm_startmeup:
	move.w		#0x2700,SR

	/*
	 * As long as the boot ROM is aligned to a 1M boundary, you can do
	 * the following.  If it is not, then use the code that places
	 * VBR at 0x00000000.
	 */

	move.l      #VECTOR_TABLE,d0
	/* moveq.l   #0,d0 */

	/* Bug in MCF52xx.  VBR only updated from A7 */
	move.l		d0,a7
	movec       a7,VBR

	/* Now point SP to good stack space. */
	move.l		#___SP_INIT,sp

	/* Invalidate the cache and disable it */
	move.l	#0x01000000,d0
	dc.l	0x4e7b0002		/* movec d0,cacr */

	/*
	 * Disable other resources
	 */
	moveq.l	#0,d0
	dc.l	0x4e7b0004		/* movec d0,ACR0 */
	dc.l	0x4e7b0005		/* movec d0,ACR1 */

	nop
	nop

	jmp			main


/*
 * Cache flushing routines for the MCF5202.  Since this is a unified
 * cache, use the same routine for both.
 *
 * This routine uses the CPUSHL instruction, however the contents of
 * the address register have a different meaning than they do in
 * 68040.  The contents specifiy a cache set and line, rather than
 * an effective address.  Also, this routine assumes that CACR[DPI] is
 * configured so that the cache line is invalidated once pushed.
 *
 * Bits 8-4 specify the row index
 * Bits 3-0 specify the line index  (only lines 0-3 valid on 5202/3)
 *
 * The MCF5202/3 has a 2K unified cache arranged as 4 sets, 32 lines per
 * set, and 16 bytes per line.
 */
cpu_cache_flush:
_cpu_cache_flush:
	nop						/* synchronize - flush store buffer */
	moveq.l	#0,d0			/* disable cache	*/
	dc.l	0x4e7b0002		/* movec d0,cacr	*/

	moveq.l	#0,d0			/* zero line counter	*/
	moveq.l	#0,d1			/* zero row  counter	*/
	move.l	d0,a0			/* initialize An	*/

rowloop:
	dc.w	0xf4e8			/* cpushl a0	*/
	add.l	#0x0010,a0		/* increment row index by 1	*/
	addq.l	#1,d1			/* increment row counter	*/
	cmpi.l	#32,d1			/* check if rows for current line are done	*/
	bne		rowloop			/* more rows to flush	*/

	moveq.l	#0,d1			/* zero row counter	*/
	addq.l	#1,d0			/* increment line counter	*/
	add.l	d0,d1			/* form row and line for An	*/
	move.l	d1,a0			/* initialize An	*/
	cmpi.l	#4,d0			/* check if lines are done	*/
	bne		rowloop

	rts


	.end