mcf5204_lo.s

motorola自己开发的针对coldfire 5272的Dbug bootloader程序

/*
 * File:	mcf5204_lo.s
 * Purpose:	Lowest level routines for MCF5204.
 *
 * Notes:	This file assembles with both Diab and GNU tools
 *
 * Author:	Eric DeVolder
 * Date:
 *
 * Modifications:
 *
 */

#ifdef _UNDERSCORE_
#define mcf5204_mbar	_mcf5204_mbar
#define mcf5204_rambar	_mcf5204_rambar
#define mcf5204_init	_mcf5204_init
#define main			_main
#endif

	.extern ___SP_INIT
	.extern	VECTOR_TABLE
	.extern mcf5204_mbar
	.extern mcf5204_rambar
	.extern mcf5204_init
	.extern	main

	.global	asm_startmeup
	.global	_asm_startmeup

	.global	cpu_cache_flush
	.global	_cpu_cache_flush

	.equ	SRAMsize,512

	.text

/*
 * This is the main entry point upon hard reset.
 */
asm_startmeup:
_asm_startmeup:
	move.w		#0x2700,SR

	/*
	 * As long as the boot ROM is aligned to a 1M boundary, you can do
	 * the following.  If it is not, then use the code that places
	 * VBR at 0x00000000.
	 */
	move.l      #VECTOR_TABLE,d0
	/* moveq.l   #0,d0 */

	/* Bug in MCF52xx.  VBR only updated from A7 */
	move.l		d0,a7
	movec       a7,VBR

	/* Invalidate the cache and disable it */
	move.l	#0x01000000,d0
	dc.l	0x4e7b0002		/* movec d0,cacr */

	/* Disable ACRs */
	moveq.l	#0,d0
	dc.l	0x4e7b0004		/* movec d0,ACR0
	dc.l	0x4e7b0005		/* movec d0,ACR1

	/* Initialize SRAMBAR */
	move.l	#0xE0000001,d0	/* locate SRAM, validate it!
	dc.l	0x4e7b0C04		/* movec d0,SRAMBAR

	/* Initialize MBAR */
	move.l	#0x00000000,d0	/* invalidate MBAR
	dc.l	0x4e7b0C0F		/* movec d0,MBAR

	nop
	nop

	/*
	 * Point SP into SRAM (temporarily).  SRAM is used as stack space
	 * while initializing the MCF5204 periphs and memory controller.
	 */
	move.l	#0xE0000000+SRAMsize,SP

	/* Obtain pointer to where MBAR is to be mapped */
	jsr		mcf5204_mbar
	move.l	d0,d6

	/* Obtain pointer to where RAMBAR is to be mapped */
	jsr		mcf5204_rambar

	/* Adjust SP to (soon to be valid) SRAM */
	move.l	d0,a0
	lea		SRAMsize(a0),SP

	/* Map RAMBAR and MBAR */
	addq.l	#1,d0			/* Set Valid bit */
	dc.l	0x4e7b0C04		/* movec d0,RAMBAR */

	move.l	d6,d0
	addq.l	#1,d0			/* Set Valid bit */
	dc.l	0x4e7b0C0F		/* movec d0,MBAR */

	/* Initialize MCF5204 periphs, etc */
	move.l	d6,-(sp)		/* pointer to internal resources */
	jsr		mcf5204_init
	lea		4(sp),sp

	/*
	 * Point SP to DRAM.  DRAM may only be visible once CS0 
	 * de-activated as global chipselect.
	 */
	move.l	#___SP_INIT,sp

	nop
	nop

	jmp		main


/*
 * MCF5204 has Icache only
 */
cpu_cache_flush:
_cpu_cache_flush:
	nop						/* sync */
	move.l	#0x01000000,d0
	dc.l	0x4e7b0002		/* movec d0,cacr */
	nop						/* sync */
	dc.l	0x4e7b0002		/* movec d0,cacr */
	rts

	.end