📄 mpc6xx.h
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/*
* File: src/include/cpu/ppc/mpc6xx/mpc6xx.h
* Purpose: Definitions common across all MPC6XX processors
*
* Notes:
*
*/
#ifndef _CPU_MPC6XX_H
#define _CPU_MPC6XX_H
/********************************************************************/
#define MPC6XX_BATU_BEPI(a) (((a)&0xFFFE0000))
#define MPC6XX_BATU_BL_128K (0x00000000)
#define MPC6XX_BATU_BL_256K (0x00000004)
#define MPC6XX_BATU_BL_512K (0x0000000C)
#define MPC6XX_BATU_BL_1M (0x0000001C)
#define MPC6XX_BATU_BL_2M (0x0000003C)
#define MPC6XX_BATU_BL_4M (0x0000007C)
#define MPC6XX_BATU_BL_8M (0x000000FC)
#define MPC6XX_BATU_BL_16M (0x000001FC)
#define MPC6XX_BATU_BL_32M (0x000003FC)
#define MPC6XX_BATU_BL_64M (0x000007FC)
#define MPC6XX_BATU_BL_128M (0x00000FFC)
#define MPC6XX_BATU_BL_256M (0x00001FFC)
#define MPC6XX_BATU_VS (0x00000002)
#define MPC6XX_BATU_VP (0x00000001)
#define MPC6XX_BATL_BRPN(a) (((a)&0xFFFE0000))
#define MPC6XX_BATL_NE (0x00000400)
#define MPC6XX_BATL_SE (0x00000200)
#define MPC6XX_BATL_W (0x00000040)
#define MPC6XX_BATL_I (0x00000020)
#define MPC6XX_BATL_M (0x00000010)
#define MPC6XX_BATL_G (0x00000008)
#define MPC6XX_BATL_P1 (0x00000002)
#define MPC6XX_BATL_P0 (0x00000001)
#define MPC6XX_SR_T0_T (0x80000000)
#define MPC6XX_SR_T0_KS (0x40000000)
#define MPC6XX_SR_T0_KP (0x20000000)
#define MPC6XX_SR_T0_N (0x10000000)
#define MPC6XX_SR_T0_VSID(a) (((a)&0x00FFFFFF))
#define MPC6XX_SR_T0_VSID_MASK (0x00FFFFFF)
#define MPC6XX_SR_T1_T (0x80000000)
#define MPC6XX_SR_T1_KS (0x40000000)
#define MPC6XX_SR_T1_KP (0x20000000)
#define MPC6XX_SR_T1_BUID(a) (((a)&0x000001FF)<<20)
#define MPC6XX_SR_T1_BUID_MASK (0x1FF00000)
#define MPC6XX_SR_T1_CSI(a) (((a)&0x000FFFFF))
#define MPC6XX_SR_T1_CSI_MASK (0x000FFFFF)
/********************************************************************/
#define MPC60X_FPSCR_FX (0x80000000)
#define MPC60X_FPSCR_FEX (0x40000000)
#define MPC60X_FPSCR_VX (0x20000000)
#define MPC60X_FPSCR_OX (0x10000000)
#define MPC60X_FPSCR_UX (0x08000000)
#define MPC60X_FPSCR_ZX (0x04000000)
#define MPC60X_FPSCR_XX (0x02000000)
#define MPC60X_FPSCR_VXSNAN (0x01000000)
#define MPC60X_FPSCR_VXISI (0x00800000)
#define MPC60X_FPSCR_VXIDI (0x00400000)
#define MPC60X_FPSCR_VXZDZ (0x00200000)
#define MPC60X_FPSCR_VXIMZ (0x00100000)
#define MPC60X_FPSCR_VXVC (0x00080000)
#define MPC60X_FPSCR_FR (0x00040000)
#define MPC60X_FPSCR_FI (0x00020000)
#define MPC60X_FPSCR_FPRF (0x0001F000)
#define MPC60X_FPSCR_VXSOFT (0x00000400)
#define MPC60X_FPSCR_VXSQRT (0x00000200)
#define MPC60X_FPSCR_VXCVI (0x00000100)
#define MPC60X_FPSCR_VE (0x00000080)
#define MPC60X_FPSCR_OE (0x00000040)
#define MPC60X_FPSCR_UE (0x00000020)
#define MPC60X_FPSCR_ZE (0x00000010)
#define MPC60X_FPSCR_XE (0x00000008)
#define MPC60X_FPSCR_RN_NEAR (0x00000000)
#define MPC60X_FPSCR_RN_ZERO (0x00000001)
#define MPC60X_FPSCR_RN_PLUS (0x00000002)
#define MPC60X_FPSCR_RN_MINUS (0x00000003)
/********************************************************************/
uint32 mpc6xx_rd_pvr (void);
void mpc6xx_wr_msr (uint32);
uint32 mpc6xx_rd_msr (void);
void mpc6xx_wr_tbl (uint32);
uint32 mpc6xx_rd_tbl (void);
void mpc6xx_wr_tbu (uint32);
uint32 mpc6xx_rd_tbu (void);
void mpc6xx_wr_ibat0u (uint32);
uint32 mpc6xx_rd_ibat0u (void);
void mpc6xx_wr_ibat0l (uint32);
uint32 mpc6xx_rd_ibat0l (void);
void mpc6xx_wr_ibat1u (uint32);
uint32 mpc6xx_rd_ibat1u (void);
void mpc6xx_wr_ibat1l (uint32);
uint32 mpc6xx_rd_ibat1l (void);
void mpc6xx_wr_ibat2u (uint32);
uint32 mpc6xx_rd_ibat2u (void);
void mpc6xx_wr_ibat2l (uint32);
uint32 mpc6xx_rd_ibat2l (void);
void mpc6xx_wr_ibat3u (uint32);
uint32 mpc6xx_rd_ibat3u (void);
void mpc6xx_wr_ibat3l (uint32);
uint32 mpc6xx_rd_ibat3l (void);
void mpc6xx_wr_dbat0u (uint32);
uint32 mpc6xx_rd_dbat0u (void);
void mpc6xx_wr_dbat0l (uint32);
uint32 mpc6xx_rd_dbat0l (void);
void mpc6xx_wr_dbat1u (uint32);
uint32 mpc6xx_rd_dbat1u (void);
void mpc6xx_wr_dbat1l (uint32);
uint32 mpc6xx_rd_dbat1l (void);
void mpc6xx_wr_dbat2u (uint32);
uint32 mpc6xx_rd_dbat2u (void);
void mpc6xx_wr_dbat2l (uint32);
uint32 mpc6xx_rd_dbat2l (void);
void mpc6xx_wr_dbat3u (uint32);
uint32 mpc6xx_rd_dbat3u (void);
void mpc6xx_wr_dbat3l (uint32);
uint32 mpc6xx_rd_dbat3l (void);
void mpc6xx_wr_sr0 (uint32);
uint32 mpc6xx_rd_sr0 (void);
void mpc6xx_wr_sr1 (uint32);
uint32 mpc6xx_rd_sr1 (void);
void mpc6xx_wr_sr2 (uint32);
uint32 mpc6xx_rd_sr2 (void);
void mpc6xx_wr_sr3 (uint32);
uint32 mpc6xx_rd_sr3 (void);
void mpc6xx_wr_sr4 (uint32);
uint32 mpc6xx_rd_sr4 (void);
void mpc6xx_wr_sr5 (uint32);
uint32 mpc6xx_rd_sr5 (void);
void mpc6xx_wr_sr6 (uint32);
uint32 mpc6xx_rd_sr6 (void);
void mpc6xx_wr_sr7 (uint32);
uint32 mpc6xx_rd_sr7 (void);
void mpc6xx_wr_sr8 (uint32);
uint32 mpc6xx_rd_sr8 (void);
void mpc6xx_wr_sr9 (uint32);
uint32 mpc6xx_rd_sr9 (void);
void mpc6xx_wr_sr10 (uint32);
uint32 mpc6xx_rd_sr10 (void);
void mpc6xx_wr_sr11 (uint32);
uint32 mpc6xx_rd_sr11 (void);
void mpc6xx_wr_sr12 (uint32);
uint32 mpc6xx_rd_sr12 (void);
void mpc6xx_wr_sr13 (uint32);
uint32 mpc6xx_rd_sr13 (void);
void mpc6xx_wr_sr14 (uint32);
uint32 mpc6xx_rd_sr14 (void);
void mpc6xx_wr_sr15 (uint32);
uint32 mpc6xx_rd_sr15 (void);
void mpc6xx_wr_sdr1 (uint32);
uint32 mpc6xx_rd_sdr1 (void);
void mpc6xx_wr_dar (uint32);
uint32 mpc6xx_rd_dar (void);
void mpc6xx_wr_dsisr (uint32);
uint32 mpc6xx_rd_dsisr (void);
void mpc6xx_wr_dec (uint32);
uint32 mpc6xx_rd_dec (void);
/********************************************************************/
#if (defined(CPU_MPC602))
#define MPC602_MSR_AP (0x00800000)
#define MPC602_MSR_SA (0x00400000)
#define MPC602_HID0_EMCP (0x80000000)
#define MPC602_HID0_SBCLK (0x08000000)
#define MPC602_HID0_ECLK (0x02000000)
#define MPC602_HID0_DOZE (0x00800000)
#define MPC602_HID0_NAP (0x00400000)
#define MPC602_HID0_SLEEP (0x00200000)
#define MPC602_HID0_DPM (0x00100000)
#define MPC602_HID0_RISEG (0x00080000)
#define MPC602_HID0_NHR (0x00010000)
#define MPC602_HID0_ICE (0x00008000)
#define MPC602_HID0_DCE (0x00004000)
#define MPC602_HID0_ILOCK (0x00002000)
#define MPC602_HID0_DLOCK (0x00001000)
#define MPC602_HID0_ICFI (0x00000800)
#define MPC602_HID0_DCFI (0x00000400)
#define MPC602_HID0_PO (0x00000080)
#define MPC602_HID0_SL (0x00000020)
#define MPC602_HID0_W (0x00000008)
#define MPC602_HID0_I (0x00000004)
#define MPC602_HID0_M (0x00000002)
#define MPC602_HID0_G (0x00000001)
#define MPC602_HID1_PC (0xF0000000)
#define MPC602_HID1_PC0 (0x80000000)
#define MPC602_HID1_PC1 (0x40000000)
#define MPC602_HID1_PC2 (0x20000000)
#define MPC602_HID1_PC3 (0x10000000)
#define MPC602_TCR_TI_2_23 (0x00000000)
#define MPC602_TCR_TI_2_24 (0x40000000)
#define MPC602_TCR_TI_2_25 (0x80000000)
#define MPC602_TCR_TI_2_26 (0xC0000000)
#define MPC602_TCR_CRE (0x20000000)
#define MPC602_TCR_L2E (0x10000000)
#define MPC602_TCR_NWE (0x08000000)
#define MPC602_TCR_WIE (0x04000000)
#define MPC602_TCR_SLT (0x02000000)
#define MPC602_IBR_IBA(a) ((a)&0xFFFF0000)
#define MPC602_IABR_CEA(a) ((a)&0xFFFFFFFC)
#define MPC602_IABR_IE (0x00000002)
/********************************************************************/
#elif (defined(CPU_MPC603))
#define MPC603_HID0_EMCP (0x80000000)
#define MPC603_HID0_EBA (0x20000000)
#define MPC603_HID0_EBD (0x10000000)
#define MPC603_HID0_SBCLK (0x08000000)
#define MPC603_HID0_EICE (0x04000000)
#define MPC603_HID0_ECLK (0x02000000)
#define MPC603_HID0_PAR (0x01000000)
#define MPC603_HID0_DOZE (0x00800000)
#define MPC603_HID0_NAP (0x00400000)
#define MPC603_HID0_SLEEP (0x00200000)
#define MPC603_HID0_DPM (0x00100000)
#define MPC603_HID0_RISEG (0x00080000)
#define MPC603_HID0_NHR (0x00010000)
#define MPC603_HID0_ICE (0x00008000)
#define MPC603_HID0_DCE (0x00004000)
#define MPC603_HID0_ILOCK (0x00002000)
#define MPC603_HID0_DLOCK (0x00001000)
#define MPC603_HID0_ICFI (0x00000800)
#define MPC603_HID0_DCI (0x00000400)
#define MPC603_HID0_FBIOB (0x00000010)
#define MPC603_HID0_NOOPTI (0x00000001)
#define MPC603_IABR_CEA(a) ((a)&0xFFFFFFFC)
#define MPC603_IABR_IE (0x00000002)
void mpc603_wr_hid0 (uint32);
uint32 mpc603_rd_hid0 (void);
void mpc603_wr_dmiss (uint32);
uint32 mpc603_rd_dmiss (void);
void mpc603_wr_dcmp (uint32);
uint32 mpc603_rd_dcmp (void);
uint32 mpc603_rd_hash1 (void);
uint32 mpc603_rd_hash2 (void);
void mpc603_wr_imiss (uint32);
uint32 mpc603_rd_imiss (void);
void mpc603_wr_icmp (uint32);
uint32 mpc603_rd_icmp (void);
void mpc603_wr_rpa (uint32);
uint32 mpc603_rd_rpa (void);
void mpc603_wr_iabr (uint32);
uint32 mpc603_rd_iabr (void);
void mpc603_wr_ear (uint32);
uint32 mpc603_rd_ear (void);
/********************************************************************/
#elif (defined(CPU_MPC603E))
#define MPC603E_IABR_CEA(a) ((a)&0xFFFFFFFC)
#define MPC603E_IABR_IE (0x00000002)
void mpc603e_wr_hid0 (uint32);
uint32 mpc603e_rd_hid0 (void);
uint32 mpc603e_rd_hid1 (void);
void mpc603e_wr_dmiss (uint32);
uint32 mpc603e_rd_dmiss (void);
void mpc603e_wr_dcmp (uint32);
uint32 mpc603e_rd_dcmp (void);
uint32 mpc603e_rd_hash1 (void);
uint32 mpc603e_rd_hash2 (void);
void mpc603e_wr_imiss (uint32);
uint32 mpc603e_rd_imiss (void);
void mpc603e_wr_icmp (uint32);
uint32 mpc603e_rd_icmp (void);
void mpc603e_wr_rpa (uint32);
uint32 mpc603e_rd_rpa (void);
void mpc603e_wr_iabr (uint32);
uint32 mpc603e_rd_iabr (void);
void mpc603e_wr_ear (uint32);
uint32 mpc603e_rd_ear (void);
/********************************************************************/
#elif (defined(CPU_MPC604))
#define MPC604_IABR_CEA(a) ((a)&0xFFFFFFFC)
#define MPC604_IABR_IE (0x00000002)
void mpc604_wr_hid0 (uint32);
uint32 mpc604_rd_hid0 (void);
uint32 mpc604_rd_pmc1 (void);
uint32 mpc604_rd_pmc2 (void);
void mpc604_wr_mmcr0 (uint32);
uint32 mpc604_rd_mmcr0 (void);
uint32 mpc604_rd_sda (void);
uint32 mpc604_rd_sia (void);
void mpc604_wr_iabr (uint32);
uint32 mpc604_rd_iabr (void);
void mpc604_wr_dabr (uint32);
uint32 mpc604_rd_dabr (void);
void mpc604_wr_ear (uint32);
uint32 mpc604_rd_ear (void);
uint32 mpc604_rd_pir (void);
/********************************************************************/
#elif (defined(CPU_MPC604e))
#include "mpc604e.h"
#define MPC604E_IABR_CEA(a) ((a)&0xFFFFFFFC)
#define MPC604E_IABR_IE (0x00000002)
uint32 mpc604e_rd_hid0 (void);
uint32 mpc604e_rd_hid1 (void);
uint32 mpc604e_rd_pmc1 (void);
uint32 mpc604e_rd_pmc2 (void);
void mpc604e_wr_mmcr0 (uint32);
uint32 mpc604e_rd_mmcr0 (void);
uint32 mpc604e_rd_sda (void);
uint32 mpc604e_rd_sia (void);
void mpc604e_wr_iabr (uint32);
uint32 mpc604e_rd_iabr (void);
void mpc604e_wr_dabr (uint32);
uint32 mpc604e_rd_dabr (void);
void mpc604e_wr_ear (uint32);
uint32 mpc604e_rd_ear (void);
uint32 mpc604e_rd_pir (void);
/********************************************************************/
#elif (defined(CPU_MPC740) || defined(CPU_MPC750))
uint32 mpc750_rd_upmc1 (void);
uint32 mpc750_rd_upmc2 (void);
uint32 mpc750_rd_upmc3 (void);
uint32 mpc750_rd_upmc4 (void);
uint32 mpc750_rd_usia (void);
uint32 mpc750_rd_ummcr0 (void);
uint32 mpc750_rd_ummcr1 (void);
void mpc750_wr_hid0 (uint32);
uint32 mpc750_rd_hid0 (void);
uint32 mpc750_rd_hid1 (void);
uint32 mpc750_rd_pmc1 (void);
uint32 mpc750_rd_pmc2 (void);
uint32 mpc750_rd_pmc3 (void);
uint32 mpc750_rd_pmc4 (void);
void mpc750_wr_mmcr0 (uint32);
uint32 mpc750_rd_mmcr0 (void);
void mpc750_wr_mmcr1 (uint32);
uint32 mpc750_rd_mmcr1 (void);
uint32 mpc750_rd_sia (void);
void mpc750_wr_thrm1 (uint32);
uint32 mpc750_rd_thrm1 (void);
void mpc750_wr_thrm2 (uint32);
uint32 mpc750_rd_thrm2 (void);
void mpc750_wr_thrm3 (uint32);
uint32 mpc750_rd_thrm3 (void);
void mpc750_wr_ictc (uint32);
uint32 mpc750_rd_ictc (void);
void mpc750_wr_l2cr (uint32);
uint32 mpc750_rd_l2cr (void);
void mpc750_wr_iabr (uint32);
uint32 mpc750_rd_iabr (void);
void mpc750_wr_dabr (uint32);
uint32 mpc750_rd_dabr (void);
void mpc750_wr_ear (uint32);
uint32 mpc750_rd_ear (void);
/********************************************************************/
#else
#error "Error: Unsupported PowerPC processor in mpc6xx.h"
#endif
/********************************************************************/
#endif /* _CPU_MPC6XX_H */
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