mpc8xx.h

motorola自己开发的针对coldfire 5272的Dbug bootloader程序

#define MPC8XX_PORTIO_PDDIR_PD8				(0x0080)
#define MPC8XX_PORTIO_PDDIR_PD9				(0x0040)
#define MPC8XX_PORTIO_PDDIR_PD10			(0x0020)
#define MPC8XX_PORTIO_PDDIR_PD11			(0x0010)
#define MPC8XX_PORTIO_PDDIR_PD12			(0x0008)
#define MPC8XX_PORTIO_PDDIR_PD13			(0x0004)
#define MPC8XX_PORTIO_PDDIR_PD14			(0x0002)
#define MPC8XX_PORTIO_PDDIR_PD15			(0x0001)

#define MPC8XX_PORTIO_PDPAR_PD0				(0x8000)
#define MPC8XX_PORTIO_PDPAR_PD1				(0x4000)
#define MPC8XX_PORTIO_PDPAR_PD2				(0x2000)
#define MPC8XX_PORTIO_PDPAR_PD3				(0x1000)
#define MPC8XX_PORTIO_PDPAR_PD4				(0x0800)
#define MPC8XX_PORTIO_PDPAR_PD5				(0x0400)
#define MPC8XX_PORTIO_PDPAR_PD6				(0x0200)
#define MPC8XX_PORTIO_PDPAR_PD7				(0x0100)
#define MPC8XX_PORTIO_PDPAR_PD8				(0x0080)
#define MPC8XX_PORTIO_PDPAR_PD9				(0x0040)
#define MPC8XX_PORTIO_PDPAR_PD10			(0x0020)
#define MPC8XX_PORTIO_PDPAR_PD11			(0x0010)
#define MPC8XX_PORTIO_PDPAR_PD12			(0x0008)
#define MPC8XX_PORTIO_PDPAR_PD13			(0x0004)
#define MPC8XX_PORTIO_PDPAR_PD14			(0x0002)
#define MPC8XX_PORTIO_PDPAR_PD15			(0x0001)

#define MPC8XX_PORTIO_PDDAT_PD0				(0x8000)
#define MPC8XX_PORTIO_PDDAT_PD1				(0x4000)
#define MPC8XX_PORTIO_PDDAT_PD2				(0x2000)
#define MPC8XX_PORTIO_PDDAT_PD3				(0x1000)
#define MPC8XX_PORTIO_PDDAT_PD4				(0x0800)
#define MPC8XX_PORTIO_PDDAT_PD5				(0x0400)
#define MPC8XX_PORTIO_PDDAT_PD6				(0x0200)
#define MPC8XX_PORTIO_PDDAT_PD7				(0x0100)
#define MPC8XX_PORTIO_PDDAT_PD8				(0x0080)
#define MPC8XX_PORTIO_PDDAT_PD9				(0x0040)
#define MPC8XX_PORTIO_PDDAT_PD10			(0x0020)
#define MPC8XX_PORTIO_PDDAT_PD11			(0x0010)
#define MPC8XX_PORTIO_PDDAT_PD12			(0x0008)
#define MPC8XX_PORTIO_PDDAT_PD13			(0x0004)
#define MPC8XX_PORTIO_PDDAT_PD14			(0x0002)
#define MPC8XX_PORTIO_PDDAT_PD15			(0x0001)

#endif /* Mpc8xx_portio */

/***********************************************************************/
#ifdef Mpc8xx_cpmtimer

/*
 * CPM Timers, CPMTIMER
 */
typedef volatile struct
{
	uint16	TGCR;		/* Timer Global Configuration Register	*/
	uint16	reserved1[(1+0x98f-0x982)/2];
	uint16	TMR1;		/* Timer 1 Mode Register				*/
	uint16	TMR2;		/* Timer 2 Mode Register				*/
	uint16	TRR1;		/* Timer 1 Reference Register			*/
	uint16	TRR2;		/* Timer 2 Reference Register			*/
	uint16	TCR1;		/* Timer 1 Capture Register				*/
	uint16	TCR2;		/* Timer 2 Capture Register				*/
	uint16	TCN1;		/* Timer 1 Counter Register				*/
	uint16	TCN2;		/* Timer 2 Counter Register				*/
	uint16	TMR3;		/* Timer 3 Mode Register				*/
	uint16	TMR4;		/* Timer 4 Mode Register				*/
	uint16	TRR3;		/* Timer 3 Reference Register			*/
	uint16	TRR4;		/* Timer 4 Reference Register			*/
	uint16	TCR3;		/* Timer 3 Capture Register				*/
	uint16	TCR4;		/* Timer 4 Capture Register				*/
	uint16	TCN3;		/* Timer 3 Counter Register				*/
	uint16	TCN4;		/* Timer 4 Counter Register				*/
	uint16	TER1;		/* Timer 1 Event Register				*/
	uint16	TER2;		/* Timer 2 Event Register				*/
	uint16	TER3;		/* Timer 3 Event Register				*/
	uint16	TER4;		/* Timer 4 Event Register				*/
	uint16	reserved[(1+0x9bf-0x9b8)/2];
} MPC8XX_CPMTIMER;

#define MPC8XX_CPMTIMER_TGCR_CAS4		(0x8000)
#define MPC8XX_CPMTIMER_TGCR_FRZ4		(0x4000)
#define MPC8XX_CPMTIMER_TGCR_STP4		(0x2000)
#define MPC8XX_CPMTIMER_TGCR_RST4		(0x1000)
#define MPC8XX_CPMTIMER_TGCR_GM2		(0x0800)
#define MPC8XX_CPMTIMER_TGCR_FRZ3		(0x0400)
#define MPC8XX_CPMTIMER_TGCR_STP3		(0x0200)
#define MPC8XX_CPMTIMER_TGCR_RST3		(0x0100)
#define MPC8XX_CPMTIMER_TGCR_CAS2		(0x0080)
#define MPC8XX_CPMTIMER_TGCR_FRZ2		(0x0040)
#define MPC8XX_CPMTIMER_TGCR_STP2		(0x0020)
#define MPC8XX_CPMTIMER_TGCR_RST2		(0x0010)
#define MPC8XX_CPMTIMER_TGCR_GM1		(0x0008)
#define MPC8XX_CPMTIMER_TGCR_FRZ1		(0x0004)
#define MPC8XX_CPMTIMER_TGCR_STP1		(0x0002)
#define MPC8XX_CPMTIMER_TGCR_RST1		(0x0001)

#define MPC8XX_CPMTIMER_TMR_PS(X)		(((X)&0x00FF)<<8)
#define MPC8XX_CPMTIMER_TMR_CE_NONE		(0x0000)
#define MPC8XX_CPMTIMER_TMR_CE_RISE		(0x0040)
#define MPC8XX_CPMTIMER_TMR_CE_FALL		(0x0080)
#define MPC8XX_CPMTIMER_TMR_CE_ANY		(0x00C0)
#define MPC8XX_CPMTIMER_TMR_OM			(0x0020)
#define MPC8XX_CPMTIMER_TMR_ORI			(0x0010)
#define MPC8XX_CPMTIMER_TMR_FRR			(0x0008)
#define MPC8XX_CPMTIMER_TMR_ICLK_CASC	(0x0000)
#define MPC8XX_CPMTIMER_TMR_ICLK_SYSCLK	(0x0002)
#define MPC8XX_CPMTIMER_TMR_ICLK_DIV16	(0x0004)
#define MPC8XX_CPMTIMER_TMR_ICLK_TIN	(0x0006)
#define MPC8XX_CPMTIMER_TMR_GE			(0x0001)

#define MPC8XX_CPMTIMER_TER_REF			(0x0002)
#define MPC8XX_CPMTIMER_TER_CAP			(0x0001)

#endif /* Mpc8xx_cpmtimer */

/***********************************************************************/
#ifdef Mpc8xx_cp

/*
 * Communications Processor, CP
 */
typedef volatile struct
{
	uint16	CPCR;		/* CP Command Register					*/
	uint16	reserved1;
	uint16	RCCR;		/* RISC Configuration Register			*/
	uint8	reserved2;
	uint8	RMDS;		/* RISC Development Support Status		*/
	uint32	RMDR;		/* RISC Microcode Develop. Support		*/
	uint16	CPMCR1;		/* RISC Controller Trap Register 1		*/
	uint16	CPMCR2;		/* RISC Controller Trap Register 2		*/
	uint16	CPMCR3;		/* RISC Controller Trap Register 3		*/
	uint16	CPMCR4;		/* RISC Controller Trap Register 4		*/
	uint8	reserved3;
	uint16	RTER;		/* RISC Timers Event Register			*/
	uint16	reserved4;
	uint16	RTMR;		/* RISC Timers Mask Register			*/
	uint16	reserved5[(1+0x9ef-0x9dc)/2];
} MPC8XX_CP;

#define MPC8XX_CP_CPCR_RST						(0x8000)
#define MPC8XX_CP_CPCR_FLG						(0x0001)
#define MPC8XX_CP_CPCR_OPCODE_INIT_RX_TX		(0x0000)
#define MPC8XX_CP_CPCR_OPCODE_INIT_RX			(0x0100)
#define MPC8XX_CP_CPCR_OPCODE_INIT_TX			(0x0200)
#define MPC8XX_CP_CPCR_OPCODE_ENTER_HUNT		(0x0300)
#define MPC8XX_CP_CPCR_OPCODE_STOP_TX			(0x0400)
#define MPC8XX_CP_CPCR_OPCODE_GR_STOP_TX		(0x0500)
#define MPC8XX_CP_CPCR_OPCODE_INIT_IDMA			(0x0500)
#define MPC8XX_CP_CPCR_OPCODE_RESTART_TX		(0x0600)
#define MPC8XX_CP_CPCR_OPCODE_CLOSE_RX_BD		(0x0700)
#define MPC8XX_CP_CPCR_OPCODE_SET_GROUP_ADDR	(0x0800)
#define MPC8XX_CP_CPCR_OPCODE_SET_TIMER			(0x0800)
#define MPC8XX_CP_CPCR_OPCODE_GCI_TIME_OUT		(0x0900)
#define MPC8XX_CP_CPCR_OPCODE_RESET_BCS			(0x0A00)
#define MPC8XX_CP_CPCR_OPCODE_GCI_ABORT_REQ		(0x0A00)
#define MPC8XX_CP_CPCR_OPCODE_STOP_IDMA			(0x0B00)
#define MPC8XX_CP_CPCR_OPCODE_INIT_DSP			(0x0C00)
#define MPC8XX_CP_CPCR_OPCODE_START_DSP			(0x0D00)

#define MPC8XX_CP_CPCR_CHANNEL_SCC1				(0x0000)
#define MPC8XX_CP_CPCR_CHANNEL_I2C				(0x0010)
#define MPC8XX_CP_CPCR_CHANNEL_IDMA1			(0x0010)
#define MPC8XX_CP_CPCR_CHANNEL_SCC2				(0x0040)
#define MPC8XX_CP_CPCR_CHANNEL_SPI				(0x0050)
#define MPC8XX_CP_CPCR_CHANNEL_IDMA2			(0x0050)
#define MPC8XX_CP_CPCR_CHANNEL_TIMERS			(0x0050)
#define MPC8XX_CP_CPCR_CHANNEL_SCC3				(0x0080)
#define MPC8XX_CP_CPCR_CHANNEL_SMC1				(0x0090)
#define MPC8XX_CP_CPCR_CHANNEL_DSP_R			(0x0090)
#define MPC8XX_CP_CPCR_CHANNEL_SCC4				(0x00C0)
#define MPC8XX_CP_CPCR_CHANNEL_SMC2				(0x00D0)
#define MPC8XX_CP_CPCR_CHANNEL_DSP_T			(0x00D0)

#define MPC8XX_CP_RCCR_TIME			(0x8000)
#define MPC8XX_CP_RCCR_TIMEP(a)		(((a)&0x3F)<<8)
#define MPC8XX_CP_RCCR_EX1M			(0x0080)
#define MPC8XX_CP_RCCR_EX0M			(0x0040)
#define MPC8XX_CP_RCCR_EX1P_H		(0x0000)
#define MPC8XX_CP_RCCR_EX1P_M		(0x0010)
#define MPC8XX_CP_RCCR_EX1P_L		(0x0020)
#define MPC8XX_CP_RCCR_EIE			(0x0008)
#define MPC8XX_CP_RCCR_SCD			(0x0004)
#define MPC8XX_CP_RCCR_ERAM_NONE	(0x0000)
#define MPC8XX_CP_RCCR_ERAM_512		(0x0001)
#define MPC8XX_CP_RCCR_ERAM_1024	(0x0002)
#define MPC8XX_CP_RCCR_ERAM_2048	(0x0003)

/* FIX ! missing RCTRx macros */

#define MPC8XX_CP_RTER_TIMER15					(0x8000)
#define MPC8XX_CP_RTER_TIMER14					(0x4000)
#define MPC8XX_CP_RTER_TIMER13					(0x2000)
#define MPC8XX_CP_RTER_TIMER12					(0x1000)
#define MPC8XX_CP_RTER_TIMER11					(0x0800)
#define MPC8XX_CP_RTER_TIMER10					(0x0400)
#define MPC8XX_CP_RTER_TIMER9					(0x0200)
#define MPC8XX_CP_RTER_TIMER8					(0x0100)
#define MPC8XX_CP_RTER_TIMER7					(0x0080)
#define MPC8XX_CP_RTER_TIMER6					(0x0040)
#define MPC8XX_CP_RTER_TIMER5					(0x0020)
#define MPC8XX_CP_RTER_TIMER4					(0x0010)
#define MPC8XX_CP_RTER_TIMER3					(0x0008)
#define MPC8XX_CP_RTER_TIMER2					(0x0004)
#define MPC8XX_CP_RTER_TIMER1					(0x0002)
#define MPC8XX_CP_RTER_TIMER0					(0x0001)

/* FIX !!! missing RTMR macros */

#endif /* Mpc8xx_cp */

/***********************************************************************/
#ifdef Mpc8xx_brgs

/*
 * Baud Rate Generators, BRGS
 */
typedef volatile struct
{
	uint32	BRGC1;		/* BRG 1 Configuration Register */
	uint32	BRGC2;		/* BRG 2 Configuration Register */
	uint32	BRGC3;		/* BRG 3 Configuration Register */
	uint32	BRGC4;		/* BRG 4 Configuration Register */
} MPC8XX_BRGS;

#define MPC8XX_BRGC_RST				(0x00020000)
#define MPC8XX_BRGC_EN				(0x00010000)
#define MPC8XX_BRGC_CLK_BRGCLK		(0x00000000)
#define MPC8XX_BRGC_CLK_CLK2		(0x00004000)
#define MPC8XX_BRGC_CLK_CLK6		(0x00008000)
#define MPC8XX_BRGC_ATB				(0x00002000)
#define MPC8XX_BRGC_DIV16			(0x00000001)

#endif /* Mpc8xx_brgs */

/***********************************************************************/
#if (defined(Mpc8xx_scc1) ||		\
	 defined(Mpc8xx_scc2) ||		\
	 defined(Mpc8xx_scc3) ||		\
	 defined(Mpc8xx_scc4))

/*
 * Serial Communications Controllers, SCC
 */
typedef volatile struct
{
	uint32	GSMR_L;		/* General Mode Register			*/
	uint32	GSMR_H;		/* General Mode Register			*/
	uint16	PSMR;		/* Protocl Specific Mode Register	*/
	uint16	reserved1;
	uint16	TODR;		/* Transmit on Demand				*/
	uint16	DSR;		/* Data Sync. Register				*/
	uint16	SCCE;		/* Event Register					*/
	uint16	reserved2;
	uint16	SCCM;		/* Mask Register					*/
	uint8	reserved3;
	uint8	SCCS;		/* Status Register					*/
	uint32	reserved4[2];
} MPC8XX_SCC;

#define MPC8XX_SCC_GSMR_L_SIR			(0x80000000)
#define MPC8XX_SCC_GSMR_L_EDGE_BOTH		(0x00000000)
#define MPC8XX_SCC_GSMR_L_EDGE_POS		(0x20000000)
#define MPC8XX_SCC_GSMR_L_EDGE_NEG		(0x40000000)
#define MPC8XX_SCC_GSMR_L_EDGE_NONE		(0x60000000)
#define MPC8XX_SCC_GSMR_L_TCI			(0x10000000)
#define MPC8XX_SCC_GSMR_L_TSNC_ACTIVE	(0x00000000)
#define MPC8XX_SCC_GSMR_L_TSNC_14BIT	(0x04000000)
#define MPC8XX_SCC_GSMR_L_TSNC_65BIT	(0x04000000)
#define MPC8XX_SCC_GSMR_L_TSNC_4BIT		(0x08000000)
#define MPC8XX_SCC_GSMR_L_TSNC_15BIT	(0x08000000)
#define MPC8XX_SCC_GSMR_L_TSNC_3BIT		(0x0C000000)
#define MPC8XX_SCC_GSMR_L_TSNC_1BIT		(0x0C000000)
#define MPC8XX_SCC_GSMR_L_RINV			(0x02000000)
#define MPC8XX_SCC_GSMR_L_TINV			(0x01000000)
#define MPC8XX_SCC_GSMR_L_TPL_NONE		(0x00000000)
#define MPC8XX_SCC_GSMR_L_TPL_8BIT		(0x00200000)
#define MPC8XX_SCC_GSMR_L_TPL_16BIT		(0x00400000)
#define MPC8XX_SCC_GSMR_L_TPL_32BIT		(0x00600000)
#define MPC8XX_SCC_GSMR_L_TPL_48BIT		(0x00800000)
#define MPC8XX_SCC_GSMR_L_TPL_64BIT		(0x00A00000)
#define MPC8XX_SCC_GSMR_L_TPL_128BIT	(0x00C00000)
#define MPC8XX_SCC_GSMR_L_TPP_00		(0x00000000)
#define MPC8XX_SCC_GSMR_L_TPP_10		(0x00080000)
#define MPC8XX_SCC_GSMR_L_TPP_01		(0x00100000)
#define MPC8XX_SCC_GSMR_L_TPP_11		(0x00180000)
#define MPC8XX_SCC_GSMR_L_TEND			(0x00040000)
#define MPC8XX_SCC_GSMR_L_TDCR_1X		(0x00000000)
#define MPC8XX_SCC_GSMR_L_TDCR_8X		(0x00010000)
#define MPC8XX_SCC_GSMR_L_TDCR_16X		(0x00020000)
#define MPC8XX_SCC_GSMR_L_TDCR_32X		(0x00030000)
#define MPC8XX_SCC_GSMR_L_RDCR_1X		(0x00000000)
#define MPC8XX_SCC_GSMR_L_RDCR_8X		(0x00004000)
#define MPC8XX_SCC_GSMR_L_RDCR_16X		(0x00008000)
#define MPC8XX_SCC_GSMR_L_RDCR_32X		(0x0000C000)
#define MPC8XX_SCC_GSMR_L_RENC_NRZ		(0x00000000)
#define MPC8XX_SCC_GSMR_L_RENC_NRZI		(0x00000800)
#define MPC8XX_SCC_GSMR_L_RENC_FM0		(0x00001000)
#define MPC8XX_SCC_GSMR_L_RENC_MAN		(0x00002000)
#define MPC8XX_SCC_GSMR_L_RENC_DIFF		(0x00003000)
#define MPC8XX_SCC_GSMR_L_TENC_NRZ		(0x00000000)
#define MPC8XX_SCC_GSMR_L_TENC_NRZI		(0x00000100)
#define MPC8XX_SCC_GSMR_L_TENC_FM0		(0x00000200)
#define MPC8XX_SCC_GSMR_L_TENC_MAN		(0x00000400)
#define MPC8XX_SCC_GSMR_L_TENC_DIFF		(0x00000600)
#define MPC8XX_SCC_GSMR_L_DIAG_NORMAL	(0x00000000)
#define MPC8XX_SCC_GSMR_L_DIAG_LOOPBACK	(0x00000040)
#define MPC8XX_SCC_GSMR_L_DIAG_ECHO		(0x00000080)
#define MPC8XX_SCC_GSMR_L_DIAG_LOOPECHO	(0x000000C0)
#define MPC8XX_SCC_GSMR_L_ENR			(0x00000020)
#define MPC8XX_SCC_GSMR_L_ENT			(0x00000010)
#define MPC8XX_SCC_GSMR_L_MODE_HDLC			(0x00000000)
#define MPC8XX_SCC_GSMR_L_MODE_APPLETALK	(0x00000002)
#define MPC8XX_SCC_GSMR_L_MODE_SS7			(0x00000003)
#define MPC8XX_SCC_GSMR_L_MODE_UART			(0x00000004)
#define MPC8XX_SCC_GSMR_L_MODE_PROFIBUS		(0x00000005)
#define MPC8XX_SCC_GSMR_L_MODE_ASYNCHDLC	(0x00000006)
#define MPC8XX_SCC_GSMR_L_MODE_V14			(0x00000007)
#define MPC8XX_SCC_GSMR_L_MODE_BISYNC		(0x00000008)
#define MPC8XX_SCC_GSMR_L_MODE_DDCMP		(0x00000009)
#define MPC8XX_SCC_GSMR_L_MODE_ETHERNET		(0x0000000C)

#define MPC8XX_SCC_GSMR_H_GDE			(0x00010000)