📄 mpc8xx.h
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#define MPC8XX_MEMC_MSTAT_PER3 (0x1000)
#define MPC8XX_MEMC_MSTAT_PER4 (0x0800)
#define MPC8XX_MEMC_MSTAT_PER5 (0x0400)
#define MPC8XX_MEMC_MSTAT_PER6 (0x0200)
#define MPC8XX_MEMC_MSTAT_PER7 (0x0100)
#define MPC8XX_MEMC_MSTAT_WPER (0x0080)
#define MPC8XX_MEMC_MPTPR_PTP_1 (0x4000)
#define MPC8XX_MEMC_MPTPR_PTP_2 (0x2000)
#define MPC8XX_MEMC_MPTPR_PTP_4 (0x1000)
#define MPC8XX_MEMC_MPTPR_PTP_8 (0x0800)
#define MPC8XX_MEMC_MPTPR_PTP_16 (0x0400)
#define MPC8XX_MEMC_MPTPR_PTP_32 (0x0200)
#define MPC8XX_MEMC_MPTPR_PTP_64 (0x0100)
#endif /* Mpc8xx_memc */
/***********************************************************************/
#ifdef Mpc8xx_sit
/*
* System Integration Timers, SIT
*/
typedef volatile struct
{
uint16 TBSCR; /* Time Base Status and Control */
uint16 reserved1;
uint32 TBREFF0; /* Time Base Reference 0 */
uint32 TBREFF1; /* Time Base Reference 1 */
uint32 reserved2[(1+0x21f-0x20c)/4];
uint16 RTCSC; /* Real Time Clock Status and Control */
uint16 reserved3;
uint32 RTC; /* Real Time Clock */
uint32 RTSEC; /* Real Time Alarm Seconds */
uint32 RTCAL; /* Real Time Alarm */
uint32 reserved4[(1+0x23f-0x230)/4];
uint16 PISCR; /* PIT Status and Control */
uint16 reserved5;
uint32 PITC; /* PIT Count */
uint32 PITR; /* PIT */
uint32 reserved6[(1+0x27f-0x24c)/4];
} MPC8XX_SIT;
#define MPC8XX_SIT_TBSCR_TBIRQ(a) (((a)&0x00FF)<<8)
#define MPC8XX_SIT_TBSCR_REFA (0x0080)
#define MPC8XX_SIT_TBSCR_REFB (0x0040)
#define MPC8XX_SIT_TBSCR_REFAE (0x0008)
#define MPC8XX_SIT_TBSCR_REFBE (0x0004)
#define MPC8XX_SIT_TBSCR_TBF (0x0002)
#define MPC8XX_SIT_TBSCR_TBE (0x0001)
#define MPC8XX_SIT_RTCSC_RTCIRQ(a) (((a)&0x00FF)<<8)
#define MPC8XX_SIT_RTCSC_SEC (0x0080)
#define MPC8XX_SIT_RTCSC_ALR (0x0040)
#define MPC8XX_SIT_RTCSC_38K (0x0010)
#define MPC8XX_SIT_RTCSC_SIE (0x0008)
#define MPC8XX_SIT_RTCSC_ALE (0x0004)
#define MPC8XX_SIT_RTCSC_RTF (0x0002)
#define MPC8XX_SIT_RTCSC_RTE (0x0001)
#define MPC8XX_SIT_PISCR_PIRQ(a) (((a)&0x00FF)<<8)
#define MPC8XX_SIT_PISCR_PS (0x0080)
#define MPC8XX_SIT_PISCR_PIE (0x0004)
#define MPC8XX_SIT_PISCR_PITF (0x0002)
#define MPC8XX_SIT_PISCR_PTE (0x0001)
#endif /* Mpc8xx_sit */
/***********************************************************************/
#ifdef Mpc8xx_clock
/*
* Clocks and Resets, CLOCK
*/
typedef volatile struct
{
uint32 SCCR; /* System Clock Control */
uint32 PLPRCR; /* PLL, Low Power and Reset Control */
uint32 RSR; /* Reset Status Register */
uint32 reserved[(1+0x2ff-0x28c)/4];
} MPC8XX_CLOCK;
#define MPC8XX_CLOCK_SCCR_COM (0x60000000)
#define MPC8XX_CLOCK_SCCR_COM_FULL (0x00000000)
#define MPC8XX_CLOCK_SCCR_COM_HALF (0x20000000)
#define MPC8XX_CLOCK_SCCR_COM_NONE (0x60000000)
#define MPC8XX_CLOCK_SCCR_TBS (0x02000000)
#define MPC8XX_CLOCK_SCCR_TBS_OSCCLK (0x00000000)
#define MPC8XX_CLOCK_SCCR_TBS_SYSCLK (0x02000000)
#define MPC8XX_CLOCK_SCCR_RTDIV (0x01000000)
#define MPC8XX_CLOCK_SCCR_RTDIV_4 (0x00000000)
#define MPC8XX_CLOCK_SCCR_RTDIV_512 (0x01000000)
#define MPC8XX_CLOCK_SCCR_RTSEL (0x00800000)
#define MPC8XX_CLOCK_SCCR_RTSEL_OSCM (0x00000000)
#define MPC8XX_CLOCK_SCCR_RTSEL_EXTCLK (0x00800000)
#define MPC8XX_CLOCK_SCCR_CRQEN (0x00400000)
#define MPC8XX_CLOCK_SCCR_CRQEN_LOWF (0x00000000)
#define MPC8XX_CLOCK_SCCR_CRQEN_HIGHF (0x00400000)
#define MPC8XX_CLOCK_SCCR_PRQEN (0x00200000)
#define MPC8XX_CLOCK_SCCR_PRQEN_LOWF (0x00000000)
#define MPC8XX_CLOCK_SCCR_PRQEN_HIGHF (0x00200000)
#define MPC8XX_CLOCK_SCCR_EBDF (0x00060000)
#define MPC8XX_CLOCK_SCCR_EBDF_GCLK2_DIV_1 (0x00000000)
#define MPC8XX_CLOCK_SCCR_EBDF_GCLK2_DIV_2 (0x00020000)
#define MPC8XX_CLOCK_SCCR_DFSYNC (0x00006000)
#define MPC8XX_CLOCK_SCCR_DFSYNC_DIV_1 (0x00000000)
#define MPC8XX_CLOCK_SCCR_DFSYNC_DIV_4 (0x00002000)
#define MPC8XX_CLOCK_SCCR_DFSYNC_DIV_16 (0x00004000)
#define MPC8XX_CLOCK_SCCR_DFSYNC_DIV_64 (0x00006000)
#define MPC8XX_CLOCK_SCCR_DFBRG (0x00001800)
#define MPC8XX_CLOCK_SCCR_DFBRG_DIV_1 (0x00000000)
#define MPC8XX_CLOCK_SCCR_DFBRG_DIV_4 (0x00000800)
#define MPC8XX_CLOCK_SCCR_DFBRG_DIV_16 (0x00001000)
#define MPC8XX_CLOCK_SCCR_DFBRG_DIV_64 (0x00001800)
#define MPC8XX_CLOCK_SCCR_DFNL (0x00000700)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_2 (0x00000000)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_4 (0x00000100)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_8 (0x00000200)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_16 (0x00000300)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_32 (0x00000400)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_64 (0x00000500)
#define MPC8XX_CLOCK_SCCR_DFNL_DIV_256 (0x00000700)
#define MPC8XX_CLOCK_SCCR_DFNH (0x000000E0)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_1 (0x00000000)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_2 (0x00000020)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_4 (0x00000040)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_8 (0x00000060)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_16 (0x00000080)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_32 (0x000000A0)
#define MPC8XX_CLOCK_SCCR_DFNH_DIV_64 (0x000000E0)
#define MPC8XX_CLOCK_PLPRCR_MF (0xFFF00000)
#define MPC8XX_CLOCK_PLPRCR_MF_N(a) (((a)&0x00000FFF) << 20)
#define MPC8XX_CLOCK_PLPRCR_SPLSS (0x00008000)
#define MPC8XX_CLOCK_PLPRCR_TEXPS (0x00004000)
#define MPC8XX_CLOCK_PLPRCR_TMIST (0x00001000)
#define MPC8XX_CLOCK_PLPRCR_CSRC_DFNH (0x00000000)
#define MPC8XX_CLOCK_PLPRCR_CSRC_DFNL (0x00000400)
#define MPC8XX_CLOCK_PLPRCR_LPM_00 (0x00000000)
#define MPC8XX_CLOCK_PLPRCR_LPM_01 (0x00000100)
#define MPC8XX_CLOCK_PLPRCR_LPM_10 (0x00000200)
#define MPC8XX_CLOCK_PLPRCR_LPM_11 (0x00000300)
#define MPC8XX_CLOCK_PLPRCR_CSR (0x00000080)
#define MPC8XX_CLOCK_PLPRCR_LOLRE (0x00000040)
#define MPC8XX_CLOCK_PLPRCR_FIOPD (0x00000020)
#define MPC8XX_CLOCK_RSR_EHRS (0x80000000)
#define MPC8XX_CLOCK_RSR_ESRS (0x40000000)
#define MPC8XX_CLOCK_RSR_LLRS (0x20000000)
#define MPC8XX_CLOCK_RSR_SWRS (0x10000000)
#define MPC8XX_CLOCK_RSR_SCRS (0x08000000)
#define MPC8XX_CLOCK_RSR_DBSRS (0x04000000)
#define MPC8XX_CLOCK_RSR_JTRS (0x02000000)
#endif /* Mpc8xx_clock */
/***********************************************************************/
#ifdef Mpc8xx_sitkey
/*
* System Integration Timers Keys, SITKEY
*/
typedef volatile struct
{
uint32 TBSCRK; /* Time Base Status and Control Key */
uint32 TBREFF0K; /* Time Base Reference 0 Key */
uint32 TBREFF1K; /* Time Base Reference 1 Key */
uint32 TBK; /* Time Base and Decrementer Key */
uint32 reserved1[(1+0x31f-0x310)/4];
uint32 RTCSCK; /* Real Time Clock Status and Control */
uint32 RTCK; /* Real Time Clock Key */
uint32 RTSECK; /* Real Time Alarm Seconds Key */
uint32 RTCALK; /* Real Time Alarm Key */
uint32 reserved2[(1+0x33f-0x330)/4];
uint32 PISCRK; /* PIT Status and Control Key */
uint32 PITCK; /* PIT Count Key */
uint32 reserved3[(1+0x37f-0x348)/4];
} MPC8XX_SITKEY;
#define MPC8XX_SITKEY_KEY_LOCK (0x00000000)
#define MPC8XX_SITKEY_KEY_UNLOCK (0x55CCAA33)
#endif /* Mpc8xx_sitkey */
/***********************************************************************/
#ifdef Mpc8xx_clockey
/*
* Clocks and Resets Keys, CLOCKEY
*/
typedef volatile struct
{
uint32 SCCRK; /* System Clock Control Key */
uint32 PLPRCRK; /* PLL, Low Power Reset Control Key */
uint32 RSRK; /* Reset, Status Register Key */
uint32 reserved1[(1+0x3ff-0x38c)/4];
/*
uint32 reserved2[(1+0x7ff-0x400)/4];
uint32 reserved3[(1+0x85f-0x800)/4];
*/
} MPC8XX_CLOCKEY;
#define MPC8XX_CLOCKEY_KEY_LOCK (0x00000000)
#define MPC8XX_CLOCKEY_KEY_UNLOCK (0x55CCAA33)
#endif /* Mpc8xx_clockey */
/***********************************************************************/
#ifdef Mpc8xx_i2c
/*
* Inter-Integrated device Communications, I2C
*/
typedef volatile struct
{
uint8 I2MOD; /* I2C Mode Register */
uint8 reserved1[3];
uint8 I2ADD; /* I2C Address Register */
uint8 reserved2[3];
uint8 I2BRG; /* I2C BRG Register */
uint8 reserved3[3];
uint8 I2COM; /* I2C Command Register */
uint8 reserved4[3];
uint8 I2CER; /* I2C Event Register */
uint8 reserved5[3];
uint8 I2CMR; /* I2C Mask Register */
uint8 reserved6[3];
uint32 reserved7[(1+0x8ff-0x878)/4];
} MPC8XX_I2C;
#define MPC8XX_I2C_I2MOD_REVD (0x20)
#define MPC8XX_I2C_I2MOD_GCD (0x10)
#define MPC8XX_I2C_I2MOD_FLT (0x08)
#define MPC8XX_I2C_I2MOD_PDIV_32 (0x00)
#define MPC8XX_I2C_I2MOD_PDIV_16 (0x02)
#define MPC8XX_I2C_I2MOD_PDIV_8 (0x04)
#define MPC8XX_I2C_I2MOD_PDIV_4 (0x06)
#define MPC8XX_I2C_I2MOD_EN (0x01)
#define MPC8XX_I2C_I2ADD_SAD(X) ((X)&0x00FE)
#define MPC8XX_I2C_I2BRG_DIV(X) ((X)&0x00FF)
#define MPC8XX_I2C_I2COM_STR (0x80)
#define MPC8XX_I2C_I2COM_MASTER (0x01)
#define MPC8XX_I2C_I2COM_SLAVE (0x00)
#define MPC8XX_I2C_I2CER_TXE (0x10)
#define MPC8XX_I2C_I2CER_BSY (0x04)
#define MPC8XX_I2C_I2CER_TXB (0x02)
#define MPC8XX_I2C_I2CER_RXB (0x01)
#define MPC8XX_I2C_I2CMR_TXE (0x10)
#define MPC8XX_I2C_I2CMR_BSY (0x04)
#define MPC8XX_I2C_I2CMR_TXB (0x02)
#define MPC8XX_I2C_I2CMR_RXB (0x01)
#endif /* Mpc8xx_i2c */
/***********************************************************************/
#ifdef Mpc8xx_dma
/*
* Directory Memory Access, DMA
*/
typedef volatile struct
{
uint32 reserved1;
uint32 SDAR; /* SDMA Address Register */
uint8 SDSR; /* SDMA Status Register */
uint8 reserved2[3];
uint8 SDMR; /* SDMA Mask Register */
uint8 reserved3[3];
uint8 IDSR1; /* IDMA1 Status Register */
uint8 reserved4[3];
uint8 IDMR1; /* IDMA1 Mask Register */
uint8 reserved5[3];
uint8 IDSR2; /* IDMA2 Status Register */
uint8 reserved6[3];
uint8 IDMR2; /* IDMA2 Mask Register */
uint8 reserved7[3];
uint32 reserved8[(1+0x92f-0x91d)/4];
} MPC8XX_DMA;
#define MPC8XX_DMA_SDSR_SBER (0x80)
#define MPC8XX_DMA_SDSR_RINT (0x40)
#define MPC8XX_DMA_SDSR_DSP2 (0x02)
#define MPC8XX_DMA_SDSR_DSP1 (0x01)
#define MPC8XX_DMA_SDMR_SBER (0x80)
#define MPC8XX_DMA_SDMR_RINT (0x40)
#define MPC8XX_DMA_SDMR_DSP2 (0x02)
#define MPC8XX_DMA_SDMR_DSP1 (0x01)
/* FIX !!! missing DMA_SDSR_xxx */
#endif /* Mpc8xx_dma */
/***********************************************************************/
#ifdef Mpc8xx_cpic
/*
* CPM Interrupt Controller, CPIC
*/
typedef volatile struct
{
uint16 CIVR; /* CP Interrupt Vector Register */
uint16 reserved1[(1+0x93f-0x932)/2];
uint32 CICR; /* Interrupt Configuration Register */
uint32 CIPR; /* Interrupt Pending Register */
uint32 CIMR; /* Interrupt Mask Register */
uint32 CISR; /* In-Service Register */
} MPC8XX_CPIC;
#define MPC8XX_CPIC_CIVR_MASK (0xFF00)
#define MPC8XX_CPIC_CIVR_IACK (0x0001)
#define MPC8XX_CPIC_CICR_SCDP_SCC1 (0x00000000)
#define MPC8XX_CPIC_CICR_SCDP_SCC2 (0x00400000)
#define MPC8XX_CPIC_CICR_SCDP_SCC3 (0x00800000)
#define MPC8XX_CPIC_CICR_SCDP_SCC4 (0x00C00000)
#define MPC8XX_CPIC_CICR_SCCP_SCC1 (0x00000000)
#define MPC8XX_CPIC_CICR_SCCP_SCC2 (0x00100000)
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