📄 mcf5206.h
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#define MCF5206_UART_UIP_CTS (0x01)
#define MCF5206_UART_UOP1_RTS (0x01)
#define MCF5206_UART_UOP0_RTS (0x01)
/***********************************************************************/
/*
* M-Bus Module, I2C
*/
#define MCF5206_I2C_IADR (0x01E0)
#define MCF5206_I2C_IFDR (0x01E4)
#define MCF5206_I2C_I2CR (0x01E8)
#define MCF5206_I2C_I2SR (0x01EC)
#define MCF5206_I2C_I2DR (0x01F0)
/* Read access macros for general use */
#define MCF5206_RD_I2C_IADR(IMMP) Mcf5206_iord(IMMP,MCF5206_I2C_IADR,8)
#define MCF5206_RD_I2C_IFDR(IMMP) Mcf5206_iord(IMMP,MCF5206_I2C_IFDR,8)
#define MCF5206_RD_I2C_I2CR(IMMP) Mcf5206_iord(IMMP,MCF5206_I2C_I2CR,8)
#define MCF5206_RD_I2C_I2SR(IMMP) Mcf5206_iord(IMMP,MCF5206_I2C_I2SR,8)
#define MCF5206_RD_I2C_I2DR(IMMP) Mcf5206_iord(IMMP,MCF5206_I2C_I2DR,8)
/* Write access macros for general use */
#define MCF5206_WR_I2C_IADR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_I2C_IADR,8,DATA)
#define MCF5206_WR_I2C_IFDR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_I2C_IFDR,8,DATA)
#define MCF5206_WR_I2C_I2CR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_I2C_I2CR,8,DATA)
#define MCF5206_WR_I2C_I2SR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_I2C_I2SR,8,DATA)
#define MCF5206_WR_I2C_I2DR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_I2C_I2DR,8,DATA)
#if 1
typedef volatile struct
{
uint8 reserved1[0x1E0];
uint8 IADR;
uint8 reserved2;
uint8 reserved3;
uint8 reserved4;
uint8 IFDR;
uint8 reserved5;
uint8 reserved6;
uint8 reserved7;
uint8 I2CR;
uint8 reserved8;
uint8 reserved9;
uint8 reserved10;
uint8 I2SR;
uint8 reserved11;
uint8 reserved12;
uint8 reserved13;
uint8 I2DR;
} MCF5206_I2C;
#endif
#define MCF5206_I2C_IADR_ADDR(a) ((a)&0xFE)
#define MCF5206_I2C_IFDR_MBC(a) ((a)&0x3F)
#define MCF5206_I2C_I2CR_MEN (0x80)
#define MCF5206_I2C_I2CR_MIEN (0x40)
#define MCF5206_I2C_I2CR_MSTA (0x20)
#define MCF5206_I2C_I2CR_MTX (0x10)
#define MCF5206_I2C_I2CR_TXAK (0x08)
#define MCF5206_I2C_I2CR_RSTA (0x04)
#define MCF5206_I2C_I2SR_MCF (0x80)
#define MCF5206_I2C_I2SR_MAAS (0x40)
#define MCF5206_I2C_I2SR_MBB (0x20)
#define MCF5206_I2C_I2SR_MAL (0x10)
#define MCF5206_I2C_I2SR_SRW (0x04)
#define MCF5206_I2C_I2SR_MIF (0x02)
#define MCF5206_I2C_I2SR_RXAK (0x01)
/***********************************************************************/
/*
* Timer Module, TIMER
*/
#define MCF5206_TIMER0_TMR (0x0100)
#define MCF5206_TIMER0_TRR (0x0104)
#define MCF5206_TIMER0_TCR (0x0108)
#define MCF5206_TIMER0_TCN (0x010C)
#define MCF5206_TIMER0_TER (0x0111)
#define MCF5206_TIMER1_TMR (0x0120)
#define MCF5206_TIMER1_TRR (0x0124)
#define MCF5206_TIMER1_TCR (0x0128)
#define MCF5206_TIMER1_TCN (0x012C)
#define MCF5206_TIMER1_TER (0x0131)
/* Read access macros for general use */
#define MCF5206_RD_TIMER0_TMR(IMMP) Mcf5206_iord(IMMP,MCF5206_TIMER0_TMR,16)
#define MCF5206_RD_TIMER0_TRR(IMMP) Mcf5206_iord(IMMP,MCF5206_TIMER0_TRR,16)
#define MCF5206_RD_TIMER0_TCR(IMMP) Mcf5206_iord(IMMP,MCF5206_TIMER0_TCR,16)
#define MCF5206_RD_TIMER0_TCN(IMMP) Mcf5206_iord(IMMP,MCF5206_TIMER0_TCN,16)
#define MCF5206_RD_TIMER0_TER(IMMP) Mcf5206_iord(IMMP,MCF5206_TIMER0_TER,8)
#define MCF5206_RD_TIMER1_TMR(IMMP) Mcf5206_iord(IMMP,MCF5206_TIMER1_TMR,16)
#define MCF5206_RD_TIMER1_TRR(IMMP) Mcf5206_iord(IMMP,MCF5206_TIMER1_TRR,16)
#define MCF5206_RD_TIMER1_TCR(IMMP) Mcf5206_iord(IMMP,MCF5206_TIMER1_TCR,16)
#define MCF5206_RD_TIMER1_TCN(IMMP) Mcf5206_iord(IMMP,MCF5206_TIMER1_TCN,16)
#define MCF5206_RD_TIMER1_TER(IMMP) Mcf5206_iord(IMMP,MCF5206_TIMER1_TER,8)
#define MCF5206_RD_TIMER_TMR(IMMP,NUM) \
Mcf5206_iord(IMMP,MCF5206_TIMER0_TMR + (NUM * 0x20),16)
#define MCF5206_RD_TIMER_TRR(IMMP,NUM) \
Mcf5206_iord(IMMP,MCF5206_TIMER0_TRR + (NUM * 0x20),16)
#define MCF5206_RD_TIMER_TCR(IMMP,NUM) \
Mcf5206_iord(IMMP,MCF5206_TIMER0_TCR + (NUM * 0x20),16)
#define MCF5206_RD_TIMER_TCN(IMMP,NUM) \
Mcf5206_iord(IMMP,MCF5206_TIMER0_TCN + (NUM * 0x20),16)
#define MCF5206_RD_TIMER_TER(IMMP,NUM) \
Mcf5206_iord(IMMP,MCF5206_TIMER0_TER + (NUM * 0x20),8)
/* Write access macros for general use */
#define MCF5206_WR_TIMER0_TMR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER0_TMR,16,DATA)
#define MCF5206_WR_TIMER0_TRR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER0_TRR,16,DATA)
#define MCF5206_WR_TIMER0_TCN(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER0_TCN,16,DATA)
#define MCF5206_WR_TIMER0_TER(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER0_TER,8,DATA)
#define MCF5206_WR_TIMER1_TMR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER1_TMR,16,DATA)
#define MCF5206_WR_TIMER1_TRR(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER1_TRR,16,DATA)
#define MCF5206_WR_TIMER1_TCN(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER1_TCN,16,DATA)
#define MCF5206_WR_TIMER1_TER(IMMP,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER1_TER,8,DATA)
#define MCF5206_WR_TIMER_TMR(IMMP,NUM,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER0_TMR + (NUM * 0x20),16,DATA)
#define MCF5206_WR_TIMER_TRR(IMMP,NUM,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER0_TRR + (NUM * 0x20),16,DATA)
#define MCF5206_WR_TIMER_TCN(IMMP,NUM,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER0_TCN + (NUM * 0x20),16,DATA)
#define MCF5206_WR_TIMER_TER(IMMP,NUM,DATA) \
Mcf5206_iowr(IMMP,MCF5206_TIMER0_TER + (NUM * 0x20),8,DATA)
#if 1
typedef volatile struct
{
uint8 reserved0[0x100];
uint16 TMR0;
uint16 reserved1;
uint16 TRR0;
uint16 reserved2;
uint16 TCR0;
uint16 reserved3;
uint16 TCN0;
uint16 reserved4;
uint8 reserved5;
uint8 TER0;
uint32 reserved6;
uint32 reserved7;
uint32 reserved8;
uint16 TMR1;
uint16 reserved9;
uint16 TRR1;
uint16 reserved10;
uint16 TCR1;
uint16 reserved11;
uint16 TCN1;
uint16 reserved12;
uint8 reserved13;
uint8 TER1;
} MCF5206_TIMER;
#endif
#define MCF5206_TIMER_TMR_PS(a) (((a)&0x00FF)<<8)
#define MCF5206_TIMER_TMR_CE_ANY (0x00C0)
#define MCF5206_TIMER_TMR_CE_RISE (0x0080)
#define MCF5206_TIMER_TMR_CE_FALL (0x0040)
#define MCF5206_TIMER_TMR_CE_NONE (0x0000)
#define MCF5206_TIMER_TMR_OM (0x0020)
#define MCF5206_TIMER_TMR_ORI (0x0010)
#define MCF5206_TIMER_TMR_FRR (0x0008)
#define MCF5206_TIMER_TMR_CLK_TIN (0x0006)
#define MCF5206_TIMER_TMR_CLK_DIV16 (0x0004)
#define MCF5206_TIMER_TMR_CLK_MSCLK (0x0002)
#define MCF5206_TIMER_TMR_CLK_STOP (0x0000)
#define MCF5206_TIMER_TMR_RST (0x0001)
#define MCF5206_TIMER_TER_REF (0x02)
#define MCF5206_TIMER_TER_CAP (0x01)
/***********************************************************************/
#if (defined(CPU_MCF5206e))
/*
* DMA Module, DMA
*/
#define MCF5206e_DMA0_SAR (0x0200)
#define MCF5206e_DMA0_DAR (0x0204)
#define MCF5206e_DMA0_DCR (0x0208)
#define MCF5206e_DMA0_BCR (0x020C)
#define MCF5206e_DMA0_DSR (0x0210)
#define MCF5206e_DMA0_DIVR (0x0214)
#define MCF5206e_DMA1_SAR (0x0240)
#define MCF5206e_DMA1_DAR (0x0244)
#define MCF5206e_DMA1_DCR (0x0248)
#define MCF5206e_DMA1_BCR (0x024C)
#define MCF5206e_DMA1_DSR (0x0250)
#define MCF5206e_DMA1_DIVR (0x0254)
/* Read access macros for general use */
#define MCF5206_RD_DMA0_SAR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA0_SAR,32)
#define MCF5206_RD_DMA0_DAR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA0_DAR,32)
#define MCF5206_RD_DMA0_DCR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA0_DCR,16)
#define MCF5206_RD_DMA0_BCR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA0_BCR,16)
#define MCF5206_RD_DMA0_DSR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA0_DSR,8)
#define MCF5206_RD_DMA0_DIVR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA0_DIVR,8)
#define MCF5206_RD_DMA1_SAR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA1_SAR,32)
#define MCF5206_RD_DMA1_DAR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA1_DAR,32)
#define MCF5206_RD_DMA1_DCR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA1_DCR,16)
#define MCF5206_RD_DMA1_BCR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA1_BCR,16)
#define MCF5206_RD_DMA1_DSR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA1_DSR,8)
#define MCF5206_RD_DMA1_DIVR(IMMP) Mcf5206_iord(IMMP,MCF5206e_DMA1_DIVR,8)
/* Write access macros for general use */
#define MCF5206_WR_DMA0_SAR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA0_SAR,32,DATA)
#define MCF5206_WR_DMA0_DAR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA0_DAR,32,DATA)
#define MCF5206_WR_DMA0_DCR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA0_DCR,16,DATA)
#define MCF5206_WR_DMA0_BCR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA0_BCR,16,DATA)
#define MCF5206_WR_DMA0_DSR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA0_DSR,8,DATA)
#define MCF5206_WR_DMA0_DIVR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA0_DIVR,8,DATA)
#define MCF5206_WR_DMA1_SAR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA1_SAR,32,DATA)
#define MCF5206_WR_DMA1_DAR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA1_DAR,32,DATA)
#define MCF5206_WR_DMA1_DCR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA1_DCR,16,DATA)
#define MCF5206_WR_DMA1_BCR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA1_BCR,16,DATA)
#define MCF5206_WR_DMA1_DSR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA1_DSR,8,DATA)
#define MCF5206_WR_DMA1_DIVR(IMMP,DATA) Mcf5206_iowr(IMMP,MCF5206e_DMA1_DIVR,8,DATA)
#if 1
typedef volatile struct
{
uint8 reserved1[0x200];
uint32 SAR0;
uint32 DAR0;
uint16 DCR0;
uint16 reserved2;
uint16 BCR0;
uint16 reserved3;
uint8 DSR0;
uint8 reserved4;
uint16 reserved5;
uint8 DIVR0;
uint8 reserved6;
uint16 reserved7;
uint32 reserved8[0xa];
uint32 SAR1;
uint32 DAR1;
uint16 DCR1;
uint16 reserved9;
uint16 BCR1;
uint16 reserved10;
uint8 DSR1;
uint8 reserved11;
uint16 reserved12;
uint8 DIVR1;
} MCF5206e_DMA;
#endif
#define MCF5206e_DMA_DCR_INT (0x8000) /* Interrupt on Completion */
#define MCF5206e_DMA_DCR_EEXT (0x4000) /* Enable External Request */
#define MCF5206e_DMA_DCR_CS (0x2000) /* Cycle Steal */
#define MCF5206e_DMA_DCR_AA (0x1000) /* Auto Align */
#define MCF5206e_DMA_DCR_BWC_DMA (0x0000) /* Bandwidth: DMA Priority */
#define MCF5206e_DMA_DCR_BWC_512 (0x0200) /* Bandwidth: 512 Bytes */
#define MCF5206e_DMA_DCR_BWC_1024 (0x0400) /* Bandwidth: 1024 Bytes */
#define MCF5206e_DMA_DCR_BWC_2048 (0x0600) /* Bandwidth: 2048 Bytes */
#define MCF5206e_DMA_DCR_BWC_4096 (0x0800) /* Bandwidth: 4096 Bytes */
#define MCF5206e_DMA_DCR_BWC_8192 (0x0a00) /* Bandwidth: 8192 Bytes */
#define MCF5206e_DMA_DCR_BWC_16384 (0x0c00) /* Bandwidth: 16384 Bytes */
#define MCF5206e_DMA_DCR_BWC_32768 (0x0e00) /* Bandwidth: 32768 Bytes */
#define MCF5206e_DMA_DCR_SAA (0x0100) /* Single Address Access */
#define MCF5206e_DMA_DCR_SRW (0x0080) /* Forces MRW Signal High */
#define MCF5206e_DMA_DCR_SINC (0x0040) /* Source Increment */
#define MCF5206e_DMA_DCR_SSIZE_LONG (0x0000) /* Source Size: Longword */
#define MCF5206e_DMA_DCR_SSIZE_BYTE (0x0010) /* Source Size: Byte */
#define MCF5206e_DMA_DCR_SSIZE_WORD (0x0020) /* Source Size: Word */
#define MCF5206e_DMA_DCR_SSIZE_LINE (0x0030) /* Source Size: Line */
#define MCF5206e_DMA_DCR_DINC (0x0008) /* Destination Increment */
#define MCF5206e_DMA_DCR_DSIZE_LONG (0x0000) /* Destination Size: Longword */
#define MCF5206e_DMA_DCR_DSIZE_BYTE (0x0002) /* Destination Size: Byte */
#define MCF5206e_DMA_DCR_DSIZE_WORD (0x0004) /* Destination Size: Word */
#define MCF5206e_DMA_DCR_START (0x0001) /* Start Transfer */
#define MCF5206e_DMA_DSR_CE (0x40) /* Configuration Error */
#define MCF5206e_DMA_DSR_BES (0x20) /* Bus Error on Source */
#define MCF5206e_DMA_DSR_BED (0x10) /* Bus Error on Destination */
#define MCF5206e_DMA_DSR_REQ (0x04) /* Request */
#define MCF5206e_DMA_DSR_BSY (0x02) /* Busy */
#define MCF5206e_DMA_DSR_DONE (0x01) /* Transaction Done */
#endif
/***********************************************************************/
#if 1
/*
* Here we put the modules together. An example access for the UART mode
* register would be: (assuming we have a pointer to the IMM):
*
* imm->uart1.UMR
*/
typedef volatile union
{
MCF5206_SIM sim;
MCF5206_PP pp;
MCF5206_UART0 uart0;
MCF5206_UART1 uart1;
MCF5206_TIMER timer;
MCF5206_CS cs;
MCF5206_DRAMC dramc;
MCF5206_I2C i2c;
#if (defined (CPU_MCF5206e))
MCF5206e_DMA dma;
#endif
} MCF5206_IMM;
#endif
/***********************************************************************/
#endif /* _CPU_MCF5206_H */
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