📄 mcf5272.h
字号:
/* Bit level definitions and macros */
#define MCF5272_QSPI_QMR_MSTR (0x8000)
#define MCF5272_QSPI_QMR_DOHIE (0x4000)
#define MCF5272_QSPI_QMR_BITS(x) (((x)&0x000F)<<10)
#define MCF5272_QSPI_QMR_CPOL (0x0200)
#define MCF5272_QSPI_QMR_CPHA (0x0100)
#define MCF5272_QSPI_QMR_BAUD(x) (((x)&0x00FF))
#define MCF5272_QSPI_QDLYR_SPE (0x80)
#define MCF5272_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8)
#define MCF5272_QSPI_QDLYR_DTL(x) (((x)&0x00FF))
#define MCF5272_QSPI_QWR_HALT (0x8000)
#define MCF5272_QSPI_QWR_WREN (0x4000)
#define MCF5272_QSPI_QWR_WRTO (0x2000)
#define MCF5272_QSPI_QWR_CSIV (0x1000)
#define MCF5272_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8)
#define MCF5272_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4)
#define MCF5272_QSPI_QWR_NEWQP(x) (((x)&0x000F))
#define MCF5272_QSPI_QIR_WCEFB (0x8000)
#define MCF5272_QSPI_QIR_ABRTB (0x4000)
#define MCF5272_QSPI_QIR_ABRTL (0x1000)
#define MCF5272_QSPI_QIR_WCEFE (0x0800)
#define MCF5272_QSPI_QIR_ABRTE (0x0400)
#define MCF5272_QSPI_QIR_SPIFE (0x0100)
#define MCF5272_QSPI_QIR_WCEF (0x0008)
#define MCF5272_QSPI_QIR_ABRT (0x0004)
#define MCF5272_QSPI_QIR_SPIF (0x0001)
#define MCF5272_QSPI_QAR_ADDR(x) (((x)&0x003F))
#define MCF5272_QSPI_QDR_DATA(x) (((x)&0xFFFF))
#define MCF5272_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8)
#define MCF5272_QSPI_QCR_CONT (0x8000)
#define MCF5272_QSPI_QCR_BITSE (0x4000)
#define MCF5272_QSPI_QCR_DT (0x2000)
#define MCF5272_QSPI_QCR_DSCK (0x1000)
#define MCF5272_QSPI_QCR_CS (((x)&0x000F)<<8)
/**********************************************************************
*
* PWM Module Registers Description
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_PWM_PWCR0 (*(vuint8 *)(void *)(&__MBAR[0x00C0]))
#define MCF5272_PWM_PWCR1 (*(vuint8 *)(void *)(&__MBAR[0x00C4]))
#define MCF5272_PWM_PWCR2 (*(vuint8 *)(void *)(&__MBAR[0x00C8]))
#define MCF5272_PWM_PWWD0 (*(vuint8 *)(void *)(&__MBAR[0x00D0]))
#define MCF5272_PWM_PWWD1 (*(vuint8 *)(void *)(&__MBAR[0x00D4]))
#define MCF5272_PWM_PWWD2 (*(vuint8 *)(void *)(&__MBAR[0x00D8]))
/**********************************************************************
*
* DMA Module Registers Description
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_DMA_DCMR (*(vuint32 *)(void *)(&__MBAR[0x00E0]))
#define MCF5272_DMA_DCIR (*(vuint16 *)(void *)(&__MBAR[0x00E6]))
#define MCF5272_DMA_DBCR (*(vuint32 *)(void *)(&__MBAR[0x00E8]))
#define MCF5272_DMA_DSAR (*(vuint32 *)(void *)(&__MBAR[0x00EC]))
#define MCF5272_DMA_DDAR (*(vuint32 *)(void *)(&__MBAR[0x00F0]))
/* Bit level definitions and macros */
#define MCF5272_DMA_DCMR_RESET (0x80000000)
#define MCF5272_DMA_DCMR_EN (0x40000000)
#define MCF5272_DMA_DCMR_RQM (0x000C0000)
#define MCF5272_DMA_DCMR_DSTM_INC (0x00002000)
#define MCF5272_DMA_DCMR_DSTT_UD (0x00000400)
#define MCF5272_DMA_DCMR_DSTT_UC (0x00000800)
#define MCF5272_DMA_DCMR_DSTT_SD (0x00001400)
#define MCF5272_DMA_DCMR_DSTT_SC (0x00001800)
#define MCF5272_DMA_DCMR_DSTS_LW (0x00000000)
#define MCF5272_DMA_DCMR_DSTS_B (0x00000100)
#define MCF5272_DMA_DCMR_DSTS_W (0x00000200)
#define MCF5272_DMA_DCMR_DSTS_LINE (0x00000300)
#define MCF5272_DMA_DCMR_SRCM_INC (0x00000020)
#define MCF5272_DMA_DCMR_SRCT_UD (0x00000004)
#define MCF5272_DMA_DCMR_SRCT_UC (0x00000008)
#define MCF5272_DMA_DCMR_SRCT_SD (0x00000014)
#define MCF5272_DMA_DCMR_SRCT_SC (0x00000018)
#define MCF5272_DMA_DCMR_SRCS_LW (0x00000000)
#define MCF5272_DMA_DCMR_SRCS_B (0x00000001)
#define MCF5272_DMA_DCMR_SRCS_W (0x00000002)
#define MCF5272_DMA_DCMR_SRCS_LINE (0x00000003)
#define MCF5272_DMA_DCIR_INVEN (0x1000)
#define MCF5272_DMA_DCIR_ASCEN (0x0800)
#define MCF5272_DMA_DCIR_TEEN (0x0200)
#define MCF5272_DMA_DCIR_TCEN (0x0100)
#define MCF5272_DMA_DCIR_INV (0x0010)
#define MCF5272_DMA_DCIR_ASC (0x0008)
#define MCF5272_DMA_DCIR_TE (0x0002)
#define MCF5272_DMA_DCIR_TC (0x0001)
/**********************************************************************
*
* UART Module Registers Description
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_UART0_UMR (*(vuint8 *)(void *)(&__MBAR[0x0100])) /* RW */
#define MCF5272_UART0_USR (*(vuint8 *)(void *)(&__MBAR[0x0104])) /* USR RO */
#define MCF5272_UART0_UCSR (*(vuint8 *)(void *)(&__MBAR[0x0104])) /* UCSR WO */
#define MCF5272_UART0_UCR (*(vuint8 *)(void *)(&__MBAR[0x0108])) /* WO */
#define MCF5272_UART0_URB (*(vuint8 *)(void *)(&__MBAR[0x010C])) /* URB RO */
#define MCF5272_UART0_UTB (*(vuint8 *)(void *)(&__MBAR[0x010C])) /* UTB WO */
#define MCF5272_UART0_UIPCR (*(vuint8 *)(void *)(&__MBAR[0x0110])) /* UIPCR RO */
#define MCF5272_UART0_UACR (*(vuint8 *)(void *)(&__MBAR[0x0110])) /* UACR WO */
#define MCF5272_UART0_UISR (*(vuint8 *)(void *)(&__MBAR[0x0114])) /* UISR RO */
#define MCF5272_UART0_UIMR (*(vuint8 *)(void *)(&__MBAR[0x0114])) /* UIMR WO */
#define MCF5272_UART0_UBG1 (*(vuint8 *)(void *)(&__MBAR[0x0118])) /* WO */
#define MCF5272_UART0_UBG2 (*(vuint8 *)(void *)(&__MBAR[0x011C])) /* WO */
#define MCF5272_UART0_UABR1 (*(vuint8 *)(void *)(&__MBAR[0x0120])) /* RO */
#define MCF5272_UART0_UABR2 (*(vuint8 *)(void *)(&__MBAR[0x0124])) /* RO */
#define MCF5272_UART0_UTFCSR (*(vuint8 *)(void *)(&__MBAR[0x0128])) /* RW */
#define MCF5272_UART0_URFCSR (*(vuint8 *)(void *)(&__MBAR[0x012C])) /* RW */
#define MCF5272_UART0_UFPD (*(vuint8 *)(void *)(&__MBAR[0x0130])) /* RW */
#define MCF5272_UART0_UIP (*(vuint8 *)(void *)(&__MBAR[0x0134])) /* RO */
#define MCF5272_UART0_UOP1 (*(vuint8 *)(void *)(&__MBAR[0x0138])) /* WO */
#define MCF5272_UART0_UOP0 (*(vuint8 *)(void *)(&__MBAR[0x013C])) /* WO */
#define MCF5272_UART1_UMR (*(vuint8 *)(void *)(&__MBAR[0x0140])) /* RW */
#define MCF5272_UART1_USR (*(vuint8 *)(void *)(&__MBAR[0x0144])) /* USR RO */
#define MCF5272_UART1_UCSR (*(vuint8 *)(void *)(&__MBAR[0x0144])) /* UCSR WO */
#define MCF5272_UART1_UCR (*(vuint8 *)(void *)(&__MBAR[0x0148])) /* WO */
#define MCF5272_UART1_URB (*(vuint8 *)(void *)(&__MBAR[0x014C])) /* URB RO */
#define MCF5272_UART1_UTB (*(vuint8 *)(void *)(&__MBAR[0x014C])) /* UTB WO */
#define MCF5272_UART1_UIPCR (*(vuint8 *)(void *)(&__MBAR[0x0150])) /* UIPCR RO */
#define MCF5272_UART1_UACR (*(vuint8 *)(void *)(&__MBAR[0x0150])) /* UACR WO */
#define MCF5272_UART1_UISR (*(vuint8 *)(void *)(&__MBAR[0x0154])) /* UISR RO */
#define MCF5272_UART1_UIMR (*(vuint8 *)(void *)(&__MBAR[0x0154])) /* UIMR WO */
#define MCF5272_UART1_UBG1 (*(vuint8 *)(void *)(&__MBAR[0x0158])) /* WO */
#define MCF5272_UART1_UBG2 (*(vuint8 *)(void *)(&__MBAR[0x015C])) /* WO */
#define MCF5272_UART1_UABR1 (*(vuint8 *)(void *)(&__MBAR[0x0160])) /* RO */
#define MCF5272_UART1_UABR2 (*(vuint8 *)(void *)(&__MBAR[0x0164])) /* RO */
#define MCF5272_UART1_UTFCSR (*(vuint8 *)(void *)(&__MBAR[0x0168])) /* RW */
#define MCF5272_UART1_URFCSR (*(vuint8 *)(void *)(&__MBAR[0x016C])) /* RW */
#define MCF5272_UART1_UFPD (*(vuint8 *)(void *)(&__MBAR[0x0170])) /* RW */
#define MCF5272_UART1_UIP (*(vuint8 *)(void *)(&__MBAR[0x0174])) /* RO */
#define MCF5272_UART1_UOP1 (*(vuint8 *)(void *)(&__MBAR[0x0178])) /* WO */
#define MCF5272_UART1_UOP0 (*(vuint8 *)(void *)(&__MBAR[0x017C])) /* WO */
/* Bit level definitions and macros */
#define MCF5272_UART_UMR1_RXRTS (0x80)
#define MCF5272_UART_UMR1_RXIRQ (0x40)
#define MCF5272_UART_UMR1_ERR (0x20)
#define MCF5272_UART_UMR1_PM_MULTI_ADDR (0x1C)
#define MCF5272_UART_UMR1_PM_MULTI_DATA (0x18)
#define MCF5272_UART_UMR1_PM_NONE (0x10)
#define MCF5272_UART_UMR1_PM_FORCE_HI (0x0C)
#define MCF5272_UART_UMR1_PM_FORCE_LO (0x08)
#define MCF5272_UART_UMR1_PM_ODD (0x04)
#define MCF5272_UART_UMR1_PM_EVEN (0x00)
#define MCF5272_UART_UMR1_BC_5 (0x00)
#define MCF5272_UART_UMR1_BC_6 (0x01)
#define MCF5272_UART_UMR1_BC_7 (0x02)
#define MCF5272_UART_UMR1_BC_8 (0x03)
#define MCF5272_UART_UMR2_CM_NORMAL (0x00)
#define MCF5272_UART_UMR2_CM_ECHO (0x40)
#define MCF5272_UART_UMR2_CM_LOCAL_LOOP (0x80)
#define MCF5272_UART_UMR2_CM_REMOTE_LOOP (0xC0)
#define MCF5272_UART_UMR2_TXRTS (0x20)
#define MCF5272_UART_UMR2_TXCTS (0x10)
#define MCF5272_UART_UMR2_STOP_BITS_1 (0x07)
#define MCF5272_UART_UMR2_STOP_BITS_15 (0x08)
#define MCF5272_UART_UMR2_STOP_BITS_2 (0x0F)
#define MCF5272_UART_UMR2_STOP_BITS(a) ((a)&0x0f) /* Stop Bit Length */
#define MCF5272_UART_USR_RB (0x80)
#define MCF5272_UART_USR_FE (0x40)
#define MCF5272_UART_USR_PE (0x20)
#define MCF5272_UART_USR_OE (0x10)
#define MCF5272_UART_USR_TXEMP (0x08)
#define MCF5272_UART_USR_TXRDY (0x04)
#define MCF5272_UART_USR_FFULL (0x02)
#define MCF5272_UART_USR_RXRDY (0x01)
#define MCF5272_UART_UCSR_RCS(a) (((a)&0x0f)<<4) /* Rx Clk Select */
#define MCF5272_UART_UCSR_TCS(a) ((a)&0x0f) /* Tx Clk Select */
#define MCF5272_UART_UCR_NONE (0x00)
#define MCF5272_UART_UCR_STOP_BREAK (0x70)
#define MCF5272_UART_UCR_START_BREAK (0x60)
#define MCF5272_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF5272_UART_UCR_RESET_ERROR (0x40)
#define MCF5272_UART_UCR_RESET_TX (0x30)
#define MCF5272_UART_UCR_RESET_RX (0x20)
#define MCF5272_UART_UCR_RESET_MR (0x10)
#define MCF5272_UART_UCR_TX_DISABLED (0x08)
#define MCF5272_UART_UCR_TX_ENABLED (0x04)
#define MCF5272_UART_UCR_RX_DISABLED (0x02)
#define MCF5272_UART_UCR_RX_ENABLED (0x01)
#define MCF5272_UART_UCCR_COS (0x10)
#define MCF5272_UART_UCCR_CTS (0x01)
#define MCF5272_UART_UACR_BRG (0x80)
#define MCF5272_UART_UACR_CTMS_TIMER (0x60)
#define MCF5272_UART_UACR_IEC (0x01)
#define MCF5272_UART_UISR_COS (0x80)
#define MCF5272_UART_UISR_DB (0x04)
#define MCF5272_UART_UISR_RXRDY (0x02)
#define MCF5272_UART_UISR_TXRDY (0x01)
#define MCF5272_UART_UIMR_COS (0x80)
#define MCF5272_UART_UIMR_DB (0x04)
#define MCF5272_UART_UIMR_FFULL (0x02)
#define MCF5272_UART_UIMR_TXRDY (0x01)
/**********************************************************************
*
* SDRAM Controller Module Registers Description
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_SDRAMC_SDCCR (*(vuint16 *)(void *)(&__MBAR[0x0182]))
#define MCF5272_SDRAMC_SDCTR (*(vuint16 *)(void *)(&__MBAR[0x0186]))
/* Bit level definitions and macros */
#define MCF5272_SDRAMC_SDCCR_MCAS_A7 (0x0 << 13)
#define MCF5272_SDRAMC_SDCCR_MCAS_A8 (0x1 << 13)
#define MCF5272_SDRAMC_SDCCR_MCAS_A9 (0x2 << 13)
#define MCF5272_SDRAMC_SDCCR_MCAS_A10 (0x3 << 13)
#define MCF5272_SDRAMC_SDCCR_BALOC_A20 (0x1 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A21 (0x2 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A22 (0x3 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A23 (0x4 << 8)
#define MCF5272_SDRAMC_SDCCR_BALOC_A24 (0x5 << 8)
#define MCF5272_SDRAMC_SDCCR_GSL (0x00000080)
#define MCF5272_SDRAMC_SDCCR_REG (0x00000010)
#define MCF5272_SDRAMC_SDCCR_INV (0x00000008)
#define MCF5272_SDRAMC_SDCCR_SLEEP (0x00000004)
#define MCF5272_SDRAMC_SDCCR_ACT (0x00000002)
#define MCF5272_SDRAMC_SDCCR_INIT (0x00000001)
#define MCF5272_SDRAMC_SDCTR_RTP_66MHz (0x3D << 10)
#define MCF5272_SDRAMC_SDCTR_RTP_48MHz (0x2B << 10)
#define MCF5272_SDRAMC_SDCTR_RTP_33MHz (0x1D << 10)
#define MCF5272_SDRAMC_SDCTR_RTP_25MHz (0x16 << 10)
#define MCF5272_SDRAMC_SDCTR_RC(x) ((x & 0x3) << 8)
#define MCF5272_SDRAMC_SDCTR_RP(x) ((x & 0x3) << 4)
#define MCF5272_SDRAMC_SDCTR_RCD(x) ((x & 0x3) << 2)
#define MCF5272_SDRAMC_SDCTR_CLT_2 (0x00000001)
#define MCF5272_SDRAMC_SDCTR_CLT_3 (0x00000002)
#define MCF5272_SDRAMC_SDCTR_CLT_4 (0x00000003)
/**********************************************************************
*
* Timer Module Registers Description
*
***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5272_TIMER0_TMR (*(vuint16 *)(void *)(&__MBAR[0x0200]))
#define MCF5272_TIMER0_TRR (*(vuint16 *)(void *)(&__MBAR[0x0204]))
#define MCF5272_TIMER0_TCR (*(vuint16 *)(void *)(&__MBAR[0x0208]))
#define MCF5272_TIMER0_TCN (*(vuint16 *)(void *)(&__MBAR[0x020C]))
#define MCF5272_TIMER0_TER (*(vuint16 *)(void *)(&__MBAR[0x0210]))
#define MCF5272_TIMER1_TMR (*(vuint16 *)(void *)(&__MBAR[0x0220]))
#define MCF5272_TIMER1_TRR (*(vuint16 *)(void *)(&__MBAR[0x0224]))
#define MCF5272_TIMER1_TCR (*(vuint16 *)(void *)(&__MBAR[0x0228]))
#define MCF5272_TIMER1_TCN (*(vuint16 *)(void *)(&__MBAR[0x022C]))
#define MCF5272_TIMER1_TER (*(vuint16 *)(void *)(&__MBAR[0x0230]))
#define MCF5272_TIMER2_TMR (*(vuint16 *)(void *)(&__MBAR[0x0240]))
#define MCF5272_TIMER2_TRR (*(vuint16 *)(void *)(&__MBAR[0x0244]))
#define MCF5272_TIMER2_TCR (*(vuint16 *)(void *)(&__MBAR[0x0248]))
#define MCF5272_TIMER2_TCN (*(vuint16 *)(void *)(&__MBAR[0x024C]))
#define MCF5272_TIMER2_TER (*(vuint16 *)(void *)(&__MBAR[0x0250]))
#define MCF5272_TIMER3_TMR (*(vuint16 *)(void *)(&__MBAR[0x0260]))
#define MCF5272_TIMER3_TRR (*(vuint16 *)(void *)(&__MBAR[0x0264]))
#define MCF5272_TIMER3_TCR (*(vuint16 *)(void *)(&__MBAR[0x0268]))
#define MCF5272_TIMER3_TCN (*(vuint16 *)(void *)(&__MBAR[0x026C]))
#define MCF5272_TIMER3_TER (*(vuint16 *)(void *)(&__MBAR[0x0270]))
#define MCF5272_TIMER_WRRR (*(vuint16 *)(void *)(&__MBAR[0x0280]))
#define MCF5272_TIMER_WIRR (*(vuint16 *)(void *)(&__MBAR[0x0284]))
#define MCF5272_TIMER_WCR (*(vuint16 *)(void *)(&__MBAR[0x0288]))
#define MCF5272_TIMER_WER (*(vuint16 *)(void *)(&__MBAR[0x028C]))
#define MCF5272_TIMER_TMR(x) (*(vuint16 *)(void *)(&__MBAR[0x0200+(x*20)]))
#define MCF5272_TIMER_TRR(x) (*(vuint16 *)(void *)(&__MBAR[0x0204+(x*20)]))
#define MCF5272_TIMER_TCR(x) (*(vuint16 *)(void *)(&__MBAR[0x0208+(x*20)]))
#define MCF5272_TIMER_TCN(x) (*(vuint16 *)(void *)(&__MBAR[0x020C+(x*20)]))
#define MCF5272_TIMER_TER(x) (*(vuint16 *)(void *)(&__MBAR[0x0210+(x*20)]))
/* Bit level definitions and macros */
#define MCF5272_TIMER_TMR_PS(a) (((a)&0x00FF)<<8)
#define MCF5272_TIMER_TMR_CE_ANY (0x00C0)
#define MCF5272_TIMER_TMR_CE_RISE (0x0080)
#define MCF5272_TIMER_TMR_CE_FALL (0x0040)
#define MCF5272_TIMER_TMR_CE_NONE (0x0000)
#define MCF5272_TIMER_TMR_OM (0x0020)
#define MCF5272_TIMER_TMR_ORI (0x0010)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -