mcf5272.h

motorola自己开发的针对coldfire 5272的Dbug bootloader程序

/*
 * File:		src/include/cpu/coldfire/mcf5272.h
 * Purpose:		MCF5272 definitions
 *
 * Notes:		This file automatically included.
 *				__MBAR must be defined in dbug/proj/<board>/src/<board>.h
 */

#ifndef _CPU_MCF5272_H
#define _CPU_MCF5272_H

/**********************************************************************
*
* System Configuration Registers
*
***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5272_SIM_MBAR		(*(vuint32  *)(void *)(&__MBAR[0x0000]))
#define MCF5272_SIM_SCR			(*(vuint16  *)(void *)(&__MBAR[0x0004]))
#define MCF5272_SIM_SPR			(*(vuint16  *)(void *)(&__MBAR[0x0006]))
#define MCF5272_SIM_PMR			(*(vuint32  *)(void *)(&__MBAR[0x0008]))
#define MCF5272_SIM_ALPR		(*(vuint16  *)(void *)(&__MBAR[0x000E]))
#define MCF5272_SIM_DIR			(*(vuint32  *)(void *)(&__MBAR[0x0010]))

/* Bit level definitions and macros */
#define MCF5272_SIM_SCR_HRST		0x1000
#define MCF5272_SIM_SCR_DRAMRST		0x3000
#define MCF5272_SIM_SCR_SWTR		0x2000
#define MCF5272_SIM_SCR_AR			0x0080
#define MCF5272_SIM_SCR_SOFT_RES	0x0040
#define MCF5272_SIM_SCR_HWWD_128	0x0000
#define MCF5272_SIM_SCR_HWWD_256	0x0001
#define MCF5272_SIM_SCR_HWWD_512	0x0002
#define MCF5272_SIM_SCR_HWWD_1024	0x0003
#define MCF5272_SIM_SCR_HWWD_2048	0x0004
#define MCF5272_SIM_SCR_HWWD_4096	0x0005
#define MCF5272_SIM_SCR_HWWD_8192	0x0006
#define MCF5272_SIM_SCR_HWWD_16384	0x0007

#define MCF5272_SIM_SPR_ADC			0x8000
#define MCF5272_SIM_SPR_ADCEN		0x0080
#define MCF5272_SIM_SPR_WPV 		0x4000
#define MCF5272_SIM_SPR_WPVEN		0x0040
#define MCF5272_SIM_SPR_SMV			0x2000
#define MCF5272_SIM_SPR_SMVEN		0x0020
#define MCF5272_SIM_SPR_SBE			0x1000
#define MCF5272_SIM_SPR_SBEEN		0x0010
#define MCF5272_SIM_SPR_HWT			0x0800
#define MCF5272_SIM_SPR_HWTEN		0x0008
#define MCF5272_SIM_SPR_RPV 		0x0400
#define MCF5272_SIM_SPR_RPVEN		0x0004
#define MCF5272_SIM_SPR_EXT			0x0200
#define MCF5272_SIM_SPR_EXTEN		0x0002
#define MCF5272_SIM_SPR_SUV			0x0100
#define MCF5272_SIM_SPR_SUVEN		0x0001

#define MCF5272_SIM_PMR_BDMPDN      0x80000000
#define MCF5272_SIM_PMR_ENETPDN     0x04000000
#define MCF5272_SIM_PMR_PLIPPDN     0x02000000
#define MCF5272_SIM_PMR_DRAMPDN     0x01000000
#define MCF5272_SIM_PMR_DMAPDN      0x00800000
#define MCF5272_SIM_PMR_PWMPDN      0x00400000
#define MCF5272_SIM_PMR_QSPIPDN     0x00200000
#define MCF5272_SIM_PMR_TIMERPDN    0x00100000
#define MCF5272_SIM_PMR_GPIOPDN     0x00080000
#define MCF5272_SIM_PMR_USBPDN      0x00040000
#define MCF5272_SIM_PMR_UART1PDN    0x00020000
#define MCF5272_SIM_PMR_UART0PDN    0x00010000
#define MCF5272_SIM_PMR_USBWK       0x00000400
#define MCF5272_SIM_PMR_UART1WK     0x00000200
#define MCF5272_SIM_PMR_UART0WK     0x00000100
#define MCF5272_SIM_PMR_MOS         0x00000020
#define MCF5272_SIM_PMR_SLPEN       0x00000010

/**********************************************************************
*
* Interrupt Controller Registers
*
***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5272_SIM_ICR1		(*(vuint32 *)(void *)(&__MBAR[0x0020]))
#define MCF5272_SIM_ICR2		(*(vuint32 *)(void *)(&__MBAR[0x0024]))
#define MCF5272_SIM_ICR3		(*(vuint32 *)(void *)(&__MBAR[0x0028]))
#define MCF5272_SIM_ICR4		(*(vuint32 *)(void *)(&__MBAR[0x002C]))
#define MCF5272_SIM_ISR			(*(vuint32 *)(void *)(&__MBAR[0x0030]))
#define MCF5272_SIM_PITR		(*(vuint32 *)(void *)(&__MBAR[0x0034]))
#define MCF5272_SIM_PIWR		(*(vuint32 *)(void *)(&__MBAR[0x0038]))
#define MCF5272_SIM_PIVR		(*(vuint8  *)(void *)(&__MBAR[0x003F]))

/* Bit level definitions and macros */
#define MCF5272_SIM_ICR_INT1_IL(a)	( 0x80000000 | (((a)&0x07)<<28)	)
#define MCF5272_SIM_ICR_INT2_IL(a)	( 0x08000000 | (((a)&0x07)<<24)	)
#define MCF5272_SIM_ICR_INT3_IL(a)	( 0x00800000 | (((a)&0x07)<<20)	)
#define MCF5272_SIM_ICR_INT4_IL(a)	( 0x00080000 | (((a)&0x07)<<16)	)
#define MCF5272_SIM_ICR_TMR0_IL(a)	( 0x00008000 | (((a)&0x07)<<12)	)
#define MCF5272_SIM_ICR_TMR1_IL(a)	( 0x00000800 | (((a)&0x07)<<8) )
#define MCF5272_SIM_ICR_TMR2_IL(a)	( 0x00000080 | (((a)&0x07)<<4) )
#define MCF5272_SIM_ICR_TMR3_IL(a)	( 0x00000008 | ((a)&0x07) )
#define MCF5272_SIM_ICR_TMR_IL(a,x)	( (0x8 | ((a)&0x07)) << ((3-x)*4))

#define MCF5272_SIM_ICR_UART0_IL(a)	( 0x80000000 | (((a)&0x07)<<28)	)
#define MCF5272_SIM_ICR_UART1_IL(a)	( 0x08000000 | (((a)&0x07)<<24)	)
#define MCF5272_SIM_ICR_PLIP_IL(a)	( 0x00800000 | (((a)&0x07)<<20)	)
#define MCF5272_SIM_ICR_PLIA_IL(a)	( 0x00080000 | (((a)&0x07)<<16)	)
#define MCF5272_SIM_ICR_USB0_IL(a)	( 0x00008000 | (((a)&0x07)<<12)	)
#define MCF5272_SIM_ICR_USB1_IL(a)	( 0x00000800 | (((a)&0x07)<<8) )
#define MCF5272_SIM_ICR_USB2_IL(a)	( 0x00000800 | (((a)&0x07)<<4) )
#define MCF5272_SIM_ICR_USB3_IL(a)	( 0x00000800 | ((a)&0x07) )

#define MCF5272_SIM_ICR_USB4_IL(a)	( 0x80000000 | (((a)&0x07)<<28)	)
#define MCF5272_SIM_ICR_USB5_IL(a)	( 0x08000000 | (((a)&0x07)<<24)	)
#define MCF5272_SIM_ICR_USB6_IL(a)	( 0x00800000 | (((a)&0x07)<<20)	)
#define MCF5272_SIM_ICR_USB7_IL(a)	( 0x00080000 | (((a)&0x07)<<16)	)
#define MCF5272_SIM_ICR_DMA_IL(a)	( 0x00008000 | (((a)&0x07)<<12)	)
#define MCF5272_SIM_ICR_ERX_IL(a)	( 0x00000800 | (((a)&0x07)<<8) )
#define MCF5272_SIM_ICR_ETX_IL(a)	( 0x00000080 | (((a)&0x07)<<4) )
#define MCF5272_SIM_ICR_ENTC_IL(a)	( 0x00000008 | ((a)&0x07) )

#define MCF5272_SIM_ICR_QSPI_IL(a)	( 0x80000000 | (((a)&0x07)<<28)	)
#define MCF5272_SIM_ICR_INT5_IL(a)	( 0x08000000 | (((a)&0x07)<<24)	)
#define MCF5272_SIM_ICR_INT6_IL(a)	( 0x00800000 | (((a)&0x07)<<20)	)
#define MCF5272_SIM_ICR_SWTO_IL(a)	( 0x00080000 | (((a)&0x07)<<16)	)

#define MCF5272_SIM_PITR_POS_EDGE	(0xF0000060)
#define MCF5272_SIM_PITR_NEG_EDGE	(0x00000000)

#define MCF5272_SIM_PIWR_INT1			(0x80000000)
#define MCF5272_SIM_PIWR_INT2			(0x40000000)
#define MCF5272_SIM_PIWR_INT3			(0x20000000)
#define MCF5272_SIM_PIWR_INT4			(0x10000000)
#define MCF5272_SIM_PIWR_TMR0			(0x08000000)
#define MCF5272_SIM_PIWR_TMR1			(0x04000000)
#define MCF5272_SIM_PIWR_TMR2			(0x02000000)
#define MCF5272_SIM_PIWR_TMR3			(0x01000000)
#define MCF5272_SIM_PIWR_UART0		(0x00800000)
#define MCF5272_SIM_PIWR_UART1		(0x00400000)
#define MCF5272_SIM_PIWR_PLIP			(0x00200000)
#define MCF5272_SIM_PIWR_PLIA			(0x00100000)
#define MCF5272_SIM_PIWR_USB_0			(0x00080000)
#define MCF5272_SIM_PIWR_USB_1			(0x00040000)
#define MCF5272_SIM_PIWR_USB_2			(0x00020000)
#define MCF5272_SIM_PIWR_USB_3			(0x00010000)
#define MCF5272_SIM_PIWR_USB_4			(0x00008000)
#define MCF5272_SIM_PIWR_USB_5			(0x00004000)
#define MCF5272_SIM_PIWR_USB_6			(0x00002000)
#define MCF5272_SIM_PIWR_USB_7			(0x00001000)
#define MCF5272_SIM_PIWR_DMA			(0x00000800)
#define MCF5272_SIM_PIWR_ERx			(0x00000400)
#define MCF5272_SIM_PIWR_ETx			(0x00000200)
#define MCF5272_SIM_PIWR_ENTC			(0x00000100)
#define MCF5272_SIM_PIWR_QSPI			(0x00000080)
#define MCF5272_SIM_PIWR_INT5			(0x00000040)
#define MCF5272_SIM_PIWR_INT6			(0x00000020)
#define MCF5272_SIM_PIWR_SWTO			(0x00000010)

#define MCF5272_SIM_PIVR_IL(a)		(((a)&0x07)<<5)
#define MCF5272_SIM_PIVR_NORMAL		(0x40)

/**********************************************************************
*
* Chip Select Registers
*
***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5272_CS_CSBR0	(*(vuint32 *)(void *)(&__MBAR[0x0040]))
#define MCF5272_CS_CSOR0	(*(vuint32 *)(void *)(&__MBAR[0x0044]))
#define MCF5272_CS_CSBR1	(*(vuint32 *)(void *)(&__MBAR[0x0048]))
#define MCF5272_CS_CSOR1	(*(vuint32 *)(void *)(&__MBAR[0x004C]))
#define MCF5272_CS_CSBR2	(*(vuint32 *)(void *)(&__MBAR[0x0050]))
#define MCF5272_CS_CSOR2	(*(vuint32 *)(void *)(&__MBAR[0x0054]))
#define MCF5272_CS_CSBR3	(*(vuint32 *)(void *)(&__MBAR[0x0058]))
#define MCF5272_CS_CSOR3	(*(vuint32 *)(void *)(&__MBAR[0x005C]))
#define MCF5272_CS_CSBR4	(*(vuint32 *)(void *)(&__MBAR[0x0060]))
#define MCF5272_CS_CSOR4	(*(vuint32 *)(void *)(&__MBAR[0x0064]))
#define MCF5272_CS_CSBR5	(*(vuint32 *)(void *)(&__MBAR[0x0068]))
#define MCF5272_CS_CSOR5	(*(vuint32 *)(void *)(&__MBAR[0x006C]))
#define MCF5272_CS_CSBR6	(*(vuint32 *)(void *)(&__MBAR[0x0070]))
#define MCF5272_CS_CSOR6	(*(vuint32 *)(void *)(&__MBAR[0x0074]))
#define MCF5272_CS_CSBR7	(*(vuint32 *)(void *)(&__MBAR[0x0078]))
#define MCF5272_CS_CSOR7	(*(vuint32 *)(void *)(&__MBAR[0x007C]))

/* Bit level definitions and macros */
#define MCF5272_CS_BR_BASE(a)			((a)&0xFFFFF000)

#define MCF5272_CS_OR_MASK_128M			(0xF8000000)
#define MCF5272_CS_OR_MASK_64M			(0xFC000000)
#define MCF5272_CS_OR_MASK_32M			(0xFE000000)
#define MCF5272_CS_OR_MASK_16M			(0xFF000000)
#define MCF5272_CS_OR_MASK_8M			(0xFF800000)
#define MCF5272_CS_OR_MASK_4M			(0xFFC00000)
#define MCF5272_CS_OR_MASK_2M			(0xFFE00000)
#define MCF5272_CS_OR_MASK_1M			(0xFFF00000)
#define MCF5272_CS_OR_MASK_512K			(0xFFF80000)
#define MCF5272_CS_OR_MASK_256K			(0xFFFC0000)
#define MCF5272_CS_OR_MASK_128K			(0xFFFE0000)
#define MCF5272_CS_OR_MASK_64K			(0xFFFF0000)
#define MCF5272_CS_OR_MASK_32K			(0xFFFF8000)
#define MCF5272_CS_OR_MASK_16K			(0xFFFFC000)
#define MCF5272_CS_OR_MASK_8K			(0xFFFFE000)
#define MCF5272_CS_OR_MASK_4K			(0xFFFFF000)
#define MCF5272_CS_OR_WS_MASK			(0x007C)
#define MCF5272_CS_OR_WS(a)				(((a)&0x1F)<<2)
#define MCF5272_CS_OR_BRST				(0x0100)
#define MCF5272_CS_OR_WR_ONLY			(0x0003)
#define MCF5272_CS_OR_RD_ONLY			(0x0001)

#define MCF5272_CS_BR_PS_8				(0x0100)
#define MCF5272_CS_BR_PS_16				(0x0200)
#define MCF5272_CS_BR_PS_32				(0x0000)
#define MCF5272_CS_BR_PS_LINE			(0x0300)
#define MCF5272_CS_BR_ROM				(0x0000)
#define MCF5272_CS_BR_SRAM				(0x0000)
#define MCF5272_CS_BR_SRAM_8			(0x0C00)
#define MCF5272_CS_BR_SDRAM				(0x0400)
#define MCF5272_CS_BR_ISA				(0x0800)
#define MCF5272_CS_BR_SV				(0x0080)
#define MCF5272_CS_BR_EN				(0x0001)

/**********************************************************************
*
* Ports Registers Description
*
***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5272_GPIO_PACNT		(*(vuint32 *)(void *)(&__MBAR[0x0080]))
#define MCF5272_GPIO_PADDR		(*(vuint16 *)(void *)(&__MBAR[0x0084]))
#define MCF5272_GPIO_PADAT		(*(vuint16 *)(void *)(&__MBAR[0x0086]))
#define MCF5272_GPIO_PBCNT		(*(vuint32 *)(void *)(&__MBAR[0x0088]))
#define MCF5272_GPIO_PBDDR		(*(vuint16 *)(void *)(&__MBAR[0x008C]))
#define MCF5272_GPIO_PBDAT		(*(vuint16 *)(void *)(&__MBAR[0x008E]))
#define MCF5272_GPIO_PCDDR		(*(vuint16 *)(void *)(&__MBAR[0x0094]))
#define MCF5272_GPIO_PCDAT		(*(vuint16 *)(void *)(&__MBAR[0x0096]))
#define MCF5272_GPIO_PDCNT		(*(vuint32 *)(void *)(&__MBAR[0x0098]))

/* Bit level definitions and macros */
#define MCF5272_GPIO_DDR15_INPUT	(~0x80)
#define MCF5272_GPIO_DDR15_OUTPUT	( 0x80)
#define MCF5272_GPIO_DDR14_INPUT	(~0x40)
#define MCF5272_GPIO_DDR14_OUTPUT	( 0x40)
#define MCF5272_GPIO_DDR13_INPUT	(~0x20)
#define MCF5272_GPIO_DDR13_OUTPUT	( 0x20)
#define MCF5272_GPIO_DDR12_INPUT	(~0x10)
#define MCF5272_GPIO_DDR12_OUTPUT	( 0x10)
#define MCF5272_GPIO_DDR11_INPUT	(~0x08)
#define MCF5272_GPIO_DDR11_OUTPUT	( 0x08)
#define MCF5272_GPIO_DDR10_INPUT	(~0x04)
#define MCF5272_GPIO_DDR10_OUTPUT	( 0x04)
#define MCF5272_GPIO_DDR9_INPUT		(~0x02)
#define MCF5272_GPIO_DDR9_OUTPUT	( 0x02)
#define MCF5272_GPIO_DDR8_INPUT		(~0x01)
#define MCF5272_GPIO_DDR8_OUTPUT	( 0x01)
#define MCF5272_GPIO_DDR7_INPUT		(~0x80)
#define MCF5272_GPIO_DDR7_OUTPUT	( 0x80)
#define MCF5272_GPIO_DDR6_INPUT		(~0x40)
#define MCF5272_GPIO_DDR6_OUTPUT	( 0x40)
#define MCF5272_GPIO_DDR5_INPUT		(~0x20)
#define MCF5272_GPIO_DDR5_OUTPUT	( 0x20)
#define MCF5272_GPIO_DDR4_INPUT		(~0x10)
#define MCF5272_GPIO_DDR4_OUTPUT	( 0x10)
#define MCF5272_GPIO_DDR3_INPUT		(~0x08)
#define MCF5272_GPIO_DDR3_OUTPUT	( 0x08)
#define MCF5272_GPIO_DDR2_INPUT		(~0x04)
#define MCF5272_GPIO_DDR2_OUTPUT	( 0x04)
#define MCF5272_GPIO_DDR1_INPUT		(~0x02)
#define MCF5272_GPIO_DDR1_OUTPUT	( 0x02)
#define MCF5272_GPIO_DDR0_INPUT		(~0x01)
#define MCF5272_GPIO_DDR0_OUTPUT	( 0x01)

#define MCF5272_GPIO_DAT15			( 0x80)
#define MCF5272_GPIO_DAT14			( 0x40)
#define MCF5272_GPIO_DAT13			( 0x20)
#define MCF5272_GPIO_DAT12			( 0x10)
#define MCF5272_GPIO_DAT11			( 0x08)
#define MCF5272_GPIO_DAT10			( 0x04)
#define MCF5272_GPIO_DAT9			( 0x02)
#define MCF5272_GPIO_DAT8			( 0x01)
#define MCF5272_GPIO_DAT7			( 0x80)
#define MCF5272_GPIO_DAT6			( 0x40)
#define MCF5272_GPIO_DAT5			( 0x20)
#define MCF5272_GPIO_DAT4			( 0x10)
#define MCF5272_GPIO_DAT3			( 0x08)
#define MCF5272_GPIO_DAT2			( 0x04)
#define MCF5272_GPIO_DAT1			( 0x02)
#define MCF5272_GPIO_DAT0			( 0x01)


/**********************************************************************
*
* QSPI Module Registers Description
*
***********************************************************************/

/* Read/Write access macros for general use */
#define MCF5272_QSPI_QMR	(*(vuint16 *)(void *)(&__MBAR[0x00A0]))
#define MCF5272_QSPI_QDLYR	(*(vuint16 *)(void *)(&__MBAR[0x00A4]))
#define MCF5272_QSPI_QWR	(*(vuint16 *)(void *)(&__MBAR[0x00A8]))
#define MCF5272_QSPI_QIR	(*(vuint16 *)(void *)(&__MBAR[0x00AC]))
#define MCF5272_QSPI_QAR	(*(vuint16 *)(void *)(&__MBAR[0x00B0]))
#define MCF5272_QSPI_QDR	(*(vuint16 *)(void *)(&__MBAR[0x00B4]))