📄 mcf5307.h
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#define MCF5307_DRAMC_DCMR_WP (0x00000100)
#define MCF5307_DRAMC_DCMR_CPU (0x00000040)
#define MCF5307_DRAMC_DCMR_AM (0x00000020)
#define MCF5307_DRAMC_DCMR_SC (0x00000010)
#define MCF5307_DRAMC_DCMR_SD (0x00000008)
#define MCF5307_DRAMC_DCMR_UC (0x00000004)
#define MCF5307_DRAMC_DCMR_UD (0x00000002)
#define MCF5307_DRAMC_DCMR_V (0x00000001)
#define MCF5307_DRAMC_DCR_RRA_2 (0x0000)
#define MCF5307_DRAMC_DCR_RRA_3 (0x0800)
#define MCF5307_DRAMC_DCR_RRA_4 (0x1000)
#define MCF5307_DRAMC_DCR_RRA_5 (0x1800)
#define MCF5307_DRAMC_DCR_RRP_1 (0x0000)
#define MCF5307_DRAMC_DCR_RRP_2 (0x0200)
#define MCF5307_DRAMC_DCR_RRP_3 (0x0400)
#define MCF5307_DRAMC_DCR_RRP_4 (0x0600)
#define MCF5307_DRAMC_DACR_CAS_1 (0x00000000)
#define MCF5307_DRAMC_DACR_CAS_2 (0x00001000)
#define MCF5307_DRAMC_DACR_CAS_3 (0x00002000)
#define MCF5307_DRAMC_DACR_CAS_4 (0x00003000)
#define MCF5307_DRAMC_DACR_RP_1 (0x00000000)
#define MCF5307_DRAMC_DACR_RP_2 (0x00000400)
#define MCF5307_DRAMC_DACR_RP_3 (0x00000800)
#define MCF5307_DRAMC_DACR_RP_4 (0x00000C00)
#define MCF5307_DRAMC_DACR_RNCN (0x00000200)
#define MCF5307_DRAMC_DACR_RCD_1 (0x00000000)
#define MCF5307_DRAMC_DACR_RCD_2 (0x00000100)
#define MCF5307_DRAMC_DACR_EDO (0x00000040)
#define MCF5307_DRAMC_DACR_PM_OFF (0x00000000)
#define MCF5307_DRAMC_DACR_PM_BURST (0x00000004)
#define MCF5307_DRAMC_DACR_PM_ON (0x0000000C)
#define MCF5307_DRAMC_DCR_COC (0x1000)
#define MCF5307_DRAMC_DCR_IS (0x0800)
#define MCF5307_DRAMC_DCR_RTIM_3 (0x0000)
#define MCF5307_DRAMC_DCR_RTIM_6 (0x0200)
#define MCF5307_DRAMC_DCR_RTIM_9 (0x0400)
#define MCF5307_DRAMC_DACR_CASL_1 (0x00000000)
#define MCF5307_DRAMC_DACR_CASL_2 (0x00001000)
#define MCF5307_DRAMC_DACR_CASL_3 (0x00002000)
#define MCF5307_DRAMC_DACR_CBM(a) (((a)&0x00000007)<<8)
#define MCF5307_DRAMC_DACR_IMRS (0x00000040)
#define MCF5307_DRAMC_DACR_IP (0x00000008)
#define MCF5307_DRAMC_DACR_PM (0x00000004)
/**********************************************************************/
/* UART Module, UART */
/**********************************************************************/
/* Read/Write access macros for general use */
#define MCF5307_UART0_UMR (*(vuint8 *)(void *)(&__MBAR[0x1C0]))
#define MCF5307_UART0_USR (*(vuint8 *)(void *)(&__MBAR[0x1C4]))
#define MCF5307_UART0_UCSR (*(vuint8 *)(void *)(&__MBAR[0x1C4]))
#define MCF5307_UART0_UCR (*(vuint8 *)(void *)(&__MBAR[0x1C8]))
#define MCF5307_UART0_URB (*(vuint8 *)(void *)(&__MBAR[0x1CC]))
#define MCF5307_UART0_UTB (*(vuint8 *)(void *)(&__MBAR[0x1CC]))
#define MCF5307_UART0_UIPCR (*(vuint8 *)(void *)(&__MBAR[0x1D0]))
#define MCF5307_UART0_UACR (*(vuint8 *)(void *)(&__MBAR[0x1D0]))
#define MCF5307_UART0_UISR (*(vuint8 *)(void *)(&__MBAR[0x1D4]))
#define MCF5307_UART0_UIMR (*(vuint8 *)(void *)(&__MBAR[0x1D4]))
#define MCF5307_UART0_UBG1 (*(vuint8 *)(void *)(&__MBAR[0x1D8]))
#define MCF5307_UART0_UBG2 (*(vuint8 *)(void *)(&__MBAR[0x1DC]))
#define MCF5307_UART0_UIVR (*(vuint8 *)(void *)(&__MBAR[0x1F0]))
#define MCF5307_UART0_UIP (*(vuint8 *)(void *)(&__MBAR[0x1F4]))
#define MCF5307_UART0_UOP1 (*(vuint8 *)(void *)(&__MBAR[0x1F8]))
#define MCF5307_UART0_UOP0 (*(vuint8 *)(void *)(&__MBAR[0x1FC]))
#define MCF5307_UART1_UMR (*(vuint8 *)(void *)(&__MBAR[0x200]))
#define MCF5307_UART1_USR (*(vuint8 *)(void *)(&__MBAR[0x204]))
#define MCF5307_UART1_UCSR (*(vuint8 *)(void *)(&__MBAR[0x204]))
#define MCF5307_UART1_UCR (*(vuint8 *)(void *)(&__MBAR[0x208]))
#define MCF5307_UART1_URB (*(vuint8 *)(void *)(&__MBAR[0x20C]))
#define MCF5307_UART1_UTB (*(vuint8 *)(void *)(&__MBAR[0x20C]))
#define MCF5307_UART1_UIPCR (*(vuint8 *)(void *)(&__MBAR[0x210]))
#define MCF5307_UART1_UACR (*(vuint8 *)(void *)(&__MBAR[0x210]))
#define MCF5307_UART1_UISR (*(vuint8 *)(void *)(&__MBAR[0x214]))
#define MCF5307_UART1_UIMR (*(vuint8 *)(void *)(&__MBAR[0x214]))
#define MCF5307_UART1_UBG1 (*(vuint8 *)(void *)(&__MBAR[0x218]))
#define MCF5307_UART1_UBG2 (*(vuint8 *)(void *)(&__MBAR[0x21C]))
#define MCF5307_UART1_UIVR (*(vuint8 *)(void *)(&__MBAR[0x230]))
#define MCF5307_UART1_UIP (*(vuint8 *)(void *)(&__MBAR[0x234]))
#define MCF5307_UART1_UOP1 (*(vuint8 *)(void *)(&__MBAR[0x238]))
#define MCF5307_UART1_UOP0 (*(vuint8 *)(void *)(&__MBAR[0x23C]))
/* Bit level definitions and macros */
#define MCF5307_UART_UMR1_RXRTS (0x80)
#define MCF5307_UART_UMR1_RXIRQ (0x40)
#define MCF5307_UART_UMR1_ERR (0x20)
#define MCF5307_UART_UMR1_PM_MULTI_ADDR (0x1C)
#define MCF5307_UART_UMR1_PM_MULTI_DATA (0x18)
#define MCF5307_UART_UMR1_PM_NONE (0x10)
#define MCF5307_UART_UMR1_PM_FORCE_HI (0x0C)
#define MCF5307_UART_UMR1_PM_FORCE_LO (0x08)
#define MCF5307_UART_UMR1_PM_ODD (0x04)
#define MCF5307_UART_UMR1_PM_EVEN (0x00)
#define MCF5307_UART_UMR1_BC_5 (0x00)
#define MCF5307_UART_UMR1_BC_6 (0x01)
#define MCF5307_UART_UMR1_BC_7 (0x02)
#define MCF5307_UART_UMR1_BC_8 (0x03)
#define MCF5307_UART_UMR2_CM_NORMAL (0x00)
#define MCF5307_UART_UMR2_CM_ECHO (0x40)
#define MCF5307_UART_UMR2_CM_LOCAL_LOOP (0x80)
#define MCF5307_UART_UMR2_CM_REMOTE_LOOP (0xC0)
#define MCF5307_UART_UMR2_TXRTS (0x20)
#define MCF5307_UART_UMR2_TXCTS (0x10)
#define MCF5307_UART_UMR2_STOP_BITS_1 (0x07)
#define MCF5307_UART_UMR2_STOP_BITS_15 (0x08)
#define MCF5307_UART_UMR2_STOP_BITS_2 (0x0F)
#define MCF5307_UART_UMR2_STOP_BITS(a) ((a)&0x0f)
#define MCF5307_UART_USR_RB (0x80)
#define MCF5307_UART_USR_FE (0x40)
#define MCF5307_UART_USR_PE (0x20)
#define MCF5307_UART_USR_OE (0x10)
#define MCF5307_UART_USR_TXEMP (0x08)
#define MCF5307_UART_USR_TXRDY (0x04)
#define MCF5307_UART_USR_FFULL (0x02)
#define MCF5307_UART_USR_RXRDY (0x01)
#define MCF5307_UART_UCSR_RCS(a) (((a)&0x0f)<<4)
#define MCF5307_UART_UCSR_TCS(a) ((a)&0x0f)
#define MCF5307_UART_UCR_NONE (0x00)
#define MCF5307_UART_UCR_STOP_BREAK (0x70)
#define MCF5307_UART_UCR_START_BREAK (0x60)
#define MCF5307_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF5307_UART_UCR_RESET_ERROR (0x40)
#define MCF5307_UART_UCR_RESET_TX (0x30)
#define MCF5307_UART_UCR_RESET_RX (0x20)
#define MCF5307_UART_UCR_RESET_MR (0x10)
#define MCF5307_UART_UCR_TX_DISABLED (0x08)
#define MCF5307_UART_UCR_TX_ENABLED (0x04)
#define MCF5307_UART_UCR_RX_DISABLED (0x02)
#define MCF5307_UART_UCR_RX_ENABLED (0x01)
#define MCF5307_UART_UCCR_COS (0x10)
#define MCF5307_UART_UCCR_CTS (0x01)
#define MCF5307_UART_UACR_BRG (0x80)
#define MCF5307_UART_UACR_CTMS_TIMER (0x60)
#define MCF5307_UART_UACR_IEC (0x01)
#define MCF5307_UART_UISR_COS (0x80)
#define MCF5307_UART_UISR_DB (0x04)
#define MCF5307_UART_UISR_RXRDY (0x02)
#define MCF5307_UART_UISR_TXRDY (0x01)
#define MCF5307_UART_UIMR_COS (0x80)
#define MCF5307_UART_UIMR_DB (0x04)
#define MCF5307_UART_UIMR_FFULL (0x02)
#define MCF5307_UART_UIMR_TXRDY (0x01)
/***********************************************************************/
/* I2C (I-squared C) Registers */
/***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5307_I2C_IADR (*(vuint8 *)(void *)(&__MBAR[0x0280]))
#define MCF5307_I2C_IFDR (*(vuint8 *)(void *)(&__MBAR[0x0284]))
#define MCF5307_I2C_I2CR (*(vuint8 *)(void *)(&__MBAR[0x0288]))
#define MCF5307_I2C_I2SR (*(vuint8 *)(void *)(&__MBAR[0x028C]))
#define MCF5307_I2C_I2DR (*(vuint8 *)(void *)(&__MBAR[0x0290]))
/* Bit level definitions and macros */
#define MCF5307_I2C_IADR_ADDR(a) (((a)&0xFE)<<0x01)
#define MCF5307_I2C_IFDR_MBC(a) ((a)&0x3F)
#define MCF5307_I2C_I2CR_MEN (0x80)
#define MCF5307_I2C_I2CR_MIEN (0x40)
#define MCF5307_I2C_I2CR_MSTA (0x20)
#define MCF5307_I2C_I2CR_MTX (0x10)
#define MCF5307_I2C_I2CR_TXAK (0x08)
#define MCF5307_I2C_I2CR_RSTA (0x04)
#define MCF5307_I2C_I2SR_MCF (0x80)
#define MCF5307_I2C_I2SR_MAAS (0x40)
#define MCF5307_I2C_I2SR_MBB (0x20)
#define MCF5307_I2C_I2SR_MAL (0x10)
#define MCF5307_I2C_I2SR_SRW (0x04)
#define MCF5307_I2C_I2SR_MIF (0x02)
#define MCF5307_I2C_I2SR_RXAK (0x01)
/***********************************************************************/
/* Timer Registers */
/***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5307_TIMER0_TMR (*(vuint16 *)(void *)(&__MBAR[0x0140]))
#define MCF5307_TIMER0_TRR (*(vuint16 *)(void *)(&__MBAR[0x0144]))
#define MCF5307_TIMER0_TCR (*(vuint16 *)(void *)(&__MBAR[0x0148]))
#define MCF5307_TIMER0_TCN (*(vuint16 *)(void *)(&__MBAR[0x014C]))
#define MCF5307_TIMER0_TER (*(vuint8 *)(void *)(&__MBAR[0x0151]))
#define MCF5307_TIMER1_TMR (*(vuint16 *)(void *)(&__MBAR[0x0180]))
#define MCF5307_TIMER1_TRR (*(vuint16 *)(void *)(&__MBAR[0x0184]))
#define MCF5307_TIMER1_TCR (*(vuint16 *)(void *)(&__MBAR[0x0188]))
#define MCF5307_TIMER1_TCN (*(vuint16 *)(void *)(&__MBAR[0x018C]))
#define MCF5307_TIMER1_TER (*(vuint8 *)(void *)(&__MBAR[0x0191]))
#define MCF5307_TIMER_TMR(x) (*(vuint16 *)(void *)(&__MBAR[0x0140+(x*40)]))
#define MCF5307_TIMER_TRR(x) (*(vuint16 *)(void *)(&__MBAR[0x0144+(x*40)]))
#define MCF5307_TIMER_TCR(x) (*(vuint16 *)(void *)(&__MBAR[0x0148+(x*40)]))
#define MCF5307_TIMER_TCN(x) (*(vuint16 *)(void *)(&__MBAR[0x014C+(x*40)]))
#define MCF5307_TIMER_TER(x) (*(vuint8 *)(void *)(&__MBAR[0x0151+(x*40)]))
/* Bit level definitions and macros */
#define MCF5307_TIMER_TMR_PS(a) (((a)&0x00FF)<<8)
#define MCF5307_TIMER_TMR_CE_ANY (0x00C0)
#define MCF5307_TIMER_TMR_CE_FALL (0x0080)
#define MCF5307_TIMER_TMR_CE_RISE (0x0040)
#define MCF5307_TIMER_TMR_CE_NONE (0x0000)
#define MCF5307_TIMER_TMR_OM (0x0020)
#define MCF5307_TIMER_TMR_ORI (0x0010)
#define MCF5307_TIMER_TMR_FRR (0x0008)
#define MCF5307_TIMER_TMR_CLK_TIN (0x0006)
#define MCF5307_TIMER_TMR_CLK_DIV16 (0x0004)
#define MCF5307_TIMER_TMR_CLK_MSCLK (0x0002)
#define MCF5307_TIMER_TMR_CLK_STOP (0x0000)
#define MCF5307_TIMER_TMR_RST (0x0001)
#define MCF5307_TIMER_TER_REF (0x02)
#define MCF5307_TIMER_TER_CAP (0x01)
/***********************************************************************/
/* DMA Registers */
/***********************************************************************/
/* Read/Write access macros for general use */
#define MCF5307_DMA0_SAR (*(vuint32 *)(void *)(&__MBAR[0x0300]))
#define MCF5307_DMA0_DAR (*(vuint32 *)(void *)(&__MBAR[0x0304]))
#define MCF5307_DMA0_DCR (*(vuint16 *)(void *)(&__MBAR[0x0308]))
#if (defined(CPU_MCF5307j20))
#define MCF5307_DMA0_BCR (*(vuint32 *)(void *)(&__MBAR[0x030C]))
#else
#define MCF5307_DMA0_BCR (*(vuint16 *)(void *)(&__MBAR[0x030C]))
#endif
#define MCF5307_DMA0_DSR (*(vuint8 *)(void *)(&__MBAR[0x0310]))
#define MCF5307_DMA0_DIVR (*(vuint8 *)(void *)(&__MBAR[0x0314]))
#define MCF5307_DMA1_SAR (*(vuint32 *)(void *)(&__MBAR[0x0340]))
#define MCF5307_DMA1_DAR (*(vuint32 *)(void *)(&__MBAR[0x0344]))
#define MCF5307_DMA1_DCR (*(vuint16 *)(void *)(&__MBAR[0x0348]))
#if (defined(CPU_MCF5307j20))
#define MCF5307_DMA1_BCR (*(vuint32 *)(void *)(&__MBAR[0x030C]))
#else
#define MCF5307_DMA1_BCR (*(vuint16 *)(void *)(&__MBAR[0x030C]))
#endif
#define MCF5307_DMA1_DSR (*(vuint8 *)(void *)(&__MBAR[0x0350]))
#define MCF5307_DMA1_DIVR (*(vuint8 *)(void *)(&__MBAR[0x0354]))
#define MCF5307_DMA2_SAR (*(vuint32 *)(void *)(&__MBAR[0x0380]))
#define MCF5307_DMA2_DAR (*(vuint32 *)(void *)(&__MBAR[0x0384]))
#define MCF5307_DMA2_DCR (*(vuint16 *)(void *)(&__MBAR[0x0388]))
#if (defined(CPU_MCF5307j20))
#define MCF5307_DMA2_BCR (*(vuint32 *)(void *)(&__MBAR[0x030C]))
#else
#define MCF5307_DMA2_BCR (*(vuint16 *)(void *)(&__MBAR[0x030C]))
#endif
#define MCF5307_DMA2_DSR (*(vuint8 *)(void *)(&__MBAR[0x0390]))
#define MCF5307_DMA2_DIVR (*(vuint8 *)(void *)(&__MBAR[0x0394]))
#define MCF5307_DMA3_SAR (*(vuint32 *)(void *)(&__MBAR[0x03C0]))
#define MCF5307_DMA3_DAR (*(vuint32 *)(void *)(&__MBAR[0x03C4]))
#define MCF5307_DMA3_DCR (*(vuint16 *)(void *)(&__MBAR[0x03C8]))
#if (defined(CPU_MCF5307j20))
#define MCF5307_DMA3_BCR (*(vuint32 *)(void *)(&__MBAR[0x030C]))
#else
#define MCF5307_DMA3_BCR (*(vuint16 *)(void *)(&__MBAR[0x030C]))
#endif
#define MCF5307_DMA3_DSR (*(vuint8 *)(void *)(&__MBAR[0x03D0]))
#define MCF5307_DMA3_DIVR (*(vuint8 *)(void *)(&__MBAR[0x03D4]))
/* Bit level definitions and macros */
#define MCF5307_DMA_DCR_INT (0x8000)
#define MCF5307_DMA_DCR_EEXT (0x4000)
#define MCF5307_DMA_DCR_CS (0x2000)
#define MCF5307_DMA_DCR_AA (0x1000)
#define MCF5307_DMA_DCR_BWC_DMA (0x0000)
#define MCF5307_DMA_DCR_BWC_512 (0x0200)
#define MCF5307_DMA_DCR_BWC_1024 (0x0400)
#define MCF5307_DMA_DCR_BWC_2048 (0x0600)
#define MCF5307_DMA_DCR_BWC_4096 (0x0800)
#define MCF5307_DMA_DCR_BWC_8192 (0x0a00)
#define MCF5307_DMA_DCR_BWC_16384 (0x0c00)
#define MCF5307_DMA_DCR_BWC_32768 (0x0e00)
#define MCF5307_DMA_DCR_SAA (0x0100)
#define MCF5307_DMA_DCR_SRW (0x0080)
#define MCF5307_DMA_DCR_SINC (0x0040)
#define MCF5307_DMA_DCR_SSIZE_LONG (0x0000)
#define MCF5307_DMA_DCR_SSIZE_BYTE (0x0010)
#define MCF5307_DMA_DCR_SSIZE_WORD (0x0020)
#define MCF5307_DMA_DCR_SSIZE_LINE (0x0030)
#define MCF5307_DMA_DCR_DINC (0x0008)
#define MCF5307_DMA_DCR_DSIZE_LONG (0x0000)
#define MCF5307_DMA_DCR_DSIZE_BYTE (0x0002)
#define MCF5307_DMA_DCR_DSIZE_WORD (0x0004)
#define MCF5307_DMA_DCR_START (0x0001)
#define MCF5307_DMA_DSR_CE (0x40)
#define MCF5307_DMA_DSR_BES (0x20)
#define MCF5307_DMA_DSR_BED (0x10)
#define MCF5307_DMA_DSR_REQ (0x04)
#define MCF5307_DMA_DSR_BSY (0x02)
#define MCF5307_DMA_DSR_DONE (0x01)
/***********************************************************************/
#endif /* _CPU_MCF5307_H */
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