📄 mcf5307.h
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/*
* File: src/include/cpu/coldfire/mcf5307.h
* Purpose: MCF5307 definitions
*
* Notes: This file automatically included.
* __MBAR must be defined in <board>.h
*/
#ifndef _CPU_MCF5307_H
#define _CPU_MCF5307_H
/**********************************************************************/
/* System Integration Module, SIM */
/**********************************************************************/
/* Read/Write access macros for general use */
#define MCF5307_SIM_RSR (*(vuint8 *)(void *)(&__MBAR[0x0000]))
#define MCF5307_SIM_SYPCR (*(vuint8 *)(void *)(&__MBAR[0x0001]))
#define MCF5307_SIM_SWIVR (*(vuint8 *)(void *)(&__MBAR[0x0002]))
#define MCF5307_SIM_SWSR (*(vuint8 *)(void *)(&__MBAR[0x0003]))
#define MCF5307_SIM_PAR (*(vuint16 *)(void *)(&__MBAR[0x0004]))
#define MCF5307_SIM_IRQPAR (*(vuint8 *)(void *)(&__MBAR[0x0006]))
#define MCF5307_SIM_PLLCR (*(vuint8 *)(void *)(&__MBAR[0x0008]))
#define MCF5307_SIM_MPARK (*(vuint8 *)(void *)(&__MBAR[0x000C]))
#define MCF5307_SIM_IPR (*(vuint32 *)(void *)(&__MBAR[0x0040]))
#define MCF5307_SIM_IMR (*(vuint32 *)(void *)(&__MBAR[0x0044]))
#define MCF5307_SIM_AVCR (*(vuint8 *)(void *)(&__MBAR[0x004B]))
#define MCF5307_SIM_ICR0 (*(vuint8 *)(void *)(&__MBAR[0x004C]))
#define MCF5307_SIM_ICR1 (*(vuint8 *)(void *)(&__MBAR[0x004D]))
#define MCF5307_SIM_ICR2 (*(vuint8 *)(void *)(&__MBAR[0x004E]))
#define MCF5307_SIM_ICR3 (*(vuint8 *)(void *)(&__MBAR[0x004F]))
#define MCF5307_SIM_ICR4 (*(vuint8 *)(void *)(&__MBAR[0x0050]))
#define MCF5307_SIM_ICR5 (*(vuint8 *)(void *)(&__MBAR[0x0051]))
#define MCF5307_SIM_ICR6 (*(vuint8 *)(void *)(&__MBAR[0x0052]))
#define MCF5307_SIM_ICR7 (*(vuint8 *)(void *)(&__MBAR[0x0053]))
#define MCF5307_SIM_ICR8 (*(vuint8 *)(void *)(&__MBAR[0x0054]))
#define MCF5307_SIM_ICR9 (*(vuint8 *)(void *)(&__MBAR[0x0055]))
/* Bit level definitions and macros */
#define MCF5307_SIM_RSR_HRST (0x80)
#define MCF5307_SIM_RSR_SWTR (0x20)
#define MCF5307_SIM_SYPCR_SWE (0x80)
#define MCF5307_SIM_SYPCR_SWRI (0x40)
#define MCF5307_SIM_SYPCR_SWT_2_9 (0x00)
#define MCF5307_SIM_SYPCR_SWT_2_11 (0x08)
#define MCF5307_SIM_SYPCR_SWT_2_13 (0x10)
#define MCF5307_SIM_SYPCR_SWT_2_15 (0x18)
#define MCF5307_SIM_SYPCR_SWT_2_18 (0x20)
#define MCF5307_SIM_SYPCR_SWT_2_20 (0x28)
#define MCF5307_SIM_SYPCR_SWT_2_22 (0x30)
#define MCF5307_SIM_SYPCR_SWT_2_24 (0x38)
#define MCF5307_SIM_SYPCR_SWTA (0x04)
#define MCF5307_SIM_SYPCR_SWTAVAL (0x02)
#define MCF5307_SIM_SWSR_55 (0x55)
#define MCF5307_SIM_SWSR_AA (0xaa)
#define MCF5307_SIM_PAR_ADDR31 (0x8000)
#define MCF5307_SIM_PAR_ADDR30 (0x4000)
#define MCF5307_SIM_PAR_ADDR29 (0x2000)
#define MCF5307_SIM_PAR_ADDR28 (0x1000)
#define MCF5307_SIM_PAR_ADDR27 (0x0800)
#define MCF5307_SIM_PAR_ADDR26 (0x0400)
#define MCF5307_SIM_PAR_ADDR25 (0x0200)
#define MCF5307_SIM_PAR_ADDR24 (0x0100)
#define MCF5307_SIM_PAR_XTIP (0x0080)
#define MCF5307_SIM_PAR_DREQ0 (0x0040)
#define MCF5307_SIM_PAR_DREQ1 (0x0020)
#define MCF5307_SIM_PAR_TM2 (0x0010)
#define MCF5307_SIM_PAR_TM1 (0x0008)
#define MCF5307_SIM_PAR_TM0 (0x0004)
#define MCF5307_SIM_PAR_TT1 (0x0002)
#define MCF5307_SIM_PAR_TT0 (0x0001)
#define MCF5307_SIM_IRQPAR_2 (0x80)
#define MCF5307_SIM_IRQPAR_1 (0x40)
#define MCF5307_SIM_IRQPAR_0 (0x20)
#define MCF5307_SIM_PLLCR_ENBSTOP (0x80)
#define MCF5307_SIM_PLLCR_PLLIPL(a) (((a)&0x07)<<4)
#define MCF5307_SIM_MPARK_PARK(a) (((a)&0x03)<<6)
#define MCF5307_SIM_MPARK_E2MCTRL (0x20)
#define MCF5307_SIM_MPARK_EARBCTRL (0x10)
#define MCF5307_SIM_MPARK_SHOWDATA (0x08)
#define MCF5307_SIM_MPARK_BCR24BIT (0x01)
#define MCF5307_SIM_IPR_DMA3 (0x00020000)
#define MCF5307_SIM_IPR_DMA2 (0x00010000)
#define MCF5307_SIM_IPR_DMA1 (0x00008000)
#define MCF5307_SIM_IPR_DMA0 (0x00004000)
#define MCF5307_SIM_IPR_UART1 (0x00002000)
#define MCF5307_SIM_IPR_UART0 (0x00001000)
#define MCF5307_SIM_IPR_I2C (0x00000800)
#define MCF5307_SIM_IPR_TIMER1 (0x00000400)
#define MCF5307_SIM_IPR_TIMER0 (0x00000200)
#define MCF5307_SIM_IPR_SWT (0x00000100)
#define MCF5307_SIM_IPR_EINT7 (0x00000080)
#define MCF5307_SIM_IPR_EINT6 (0x00000040)
#define MCF5307_SIM_IPR_EINT5 (0x00000020)
#define MCF5307_SIM_IPR_EINT4 (0x00000010)
#define MCF5307_SIM_IPR_EINT3 (0x00000008)
#define MCF5307_SIM_IPR_EINT2 (0x00000004)
#define MCF5307_SIM_IPR_EINT1 (0x00000002)
#define MCF5307_SIM_IMR_DMA3 (0x00020000)
#define MCF5307_SIM_IMR_DMA2 (0x00010000)
#define MCF5307_SIM_IMR_DMA1 (0x00008000)
#define MCF5307_SIM_IMR_DMA0 (0x00004000)
#define MCF5307_SIM_IMR_UART1 (0x00002000)
#define MCF5307_SIM_IMR_UART0 (0x00001000)
#define MCF5307_SIM_IMR_I2C (0x00000800)
#define MCF5307_SIM_IMR_TIMER1 (0x00000400)
#define MCF5307_SIM_IMR_TIMER0 (0x00000200)
#define MCF5307_SIM_IMR_SWT (0x00000100)
#define MCF5307_SIM_IMR_EINT7 (0x00000080)
#define MCF5307_SIM_IMR_EINT6 (0x00000040)
#define MCF5307_SIM_IMR_EINT5 (0x00000020)
#define MCF5307_SIM_IMR_EINT4 (0x00000010)
#define MCF5307_SIM_IMR_EINT3 (0x00000008)
#define MCF5307_SIM_IMR_EINT2 (0x00000004)
#define MCF5307_SIM_IMR_EINT1 (0x00000002)
#define MCF5307_SIM_AVCR_AVEC7 (0x80)
#define MCF5307_SIM_AVCR_AVEC6 (0x40)
#define MCF5307_SIM_AVCR_AVEC5 (0x20)
#define MCF5307_SIM_AVCR_AVEC4 (0x10)
#define MCF5307_SIM_AVCR_AVEC3 (0x08)
#define MCF5307_SIM_AVCR_AVEC2 (0x04)
#define MCF5307_SIM_AVCR_AVEC1 (0x02)
#define MCF5307_SIM_AVCR_BLK (0x01)
#define MCF5307_SIM_ICR_AVEC (0x80)
#define MCF5307_SIM_ICR_IL(a) (((a)&0x07)<<2)
#define MCF5307_SIM_ICR_IP_EXT (0x02)
#define MCF5307_SIM_ICR_IP_INT (0x01)
/**********************************************************************/
/* Chip-Select Module, CS */
/**********************************************************************/
/* Read/Write access macros for general use */
#if (defined(CPU_MCF5307j20))
#define MCF5307_CS_CSAR0 (*(vuint16 *)(void *)(&__MBAR[0x0080]))
#define MCF5307_CS_CSMR0 (*(vuint32 *)(void *)(&__MBAR[0x0084]))
#define MCF5307_CS_CSCR0 (*(vuint16 *)(void *)(&__MBAR[0x008A]))
#define MCF5307_CS_CSAR1 (*(vuint16 *)(void *)(&__MBAR[0x008C]))
#define MCF5307_CS_CSMR1 (*(vuint32 *)(void *)(&__MBAR[0x0090]))
#define MCF5307_CS_CSCR1 (*(vuint16 *)(void *)(&__MBAR[0x0096]))
#define MCF5307_CS_CSAR2 (*(vuint16 *)(void *)(&__MBAR[0x0098]))
#define MCF5307_CS_CSMR2 (*(vuint32 *)(void *)(&__MBAR[0x009C]))
#define MCF5307_CS_CSCR2 (*(vuint16 *)(void *)(&__MBAR[0x00A2]))
#define MCF5307_CS_CSAR3 (*(vuint16 *)(void *)(&__MBAR[0x00A4]))
#define MCF5307_CS_CSMR3 (*(vuint32 *)(void *)(&__MBAR[0x00A8]))
#define MCF5307_CS_CSCR3 (*(vuint16 *)(void *)(&__MBAR[0x00AE]))
#define MCF5307_CS_CSAR4 (*(vuint16 *)(void *)(&__MBAR[0x00B0]))
#define MCF5307_CS_CSMR4 (*(vuint32 *)(void *)(&__MBAR[0x00B4]))
#define MCF5307_CS_CSCR4 (*(vuint16 *)(void *)(&__MBAR[0x00BA]))
#define MCF5307_CS_CSAR5 (*(vuint16 *)(void *)(&__MBAR[0x00BC]))
#define MCF5307_CS_CSMR5 (*(vuint32 *)(void *)(&__MBAR[0x00C0]))
#define MCF5307_CS_CSCR5 (*(vuint16 *)(void *)(&__MBAR[0x00C6]))
#define MCF5307_CS_CSAR6 (*(vuint16 *)(void *)(&__MBAR[0x00C8]))
#define MCF5307_CS_CSMR6 (*(vuint32 *)(void *)(&__MBAR[0x00CC]))
#define MCF5307_CS_CSCR6 (*(vuint16 *)(void *)(&__MBAR[0x00D2]))
#define MCF5307_CS_CSAR7 (*(vuint16 *)(void *)(&__MBAR[0x00D4]))
#define MCF5307_CS_CSMR7 (*(vuint32 *)(void *)(&__MBAR[0x00D8]))
#define MCF5307_CS_CSCR7 (*(vuint16 *)(void *)(&__MBAR[0x00DE]))
#else /* H55J mask */
#define MCF5307_CS_CSAR0 (*(vuint16 *)(void *)(&__MBAR[0x0080]))
#define MCF5307_CS_CSMR0 (*(vuint32 *)(void *)(&__MBAR[0x0084]))
#define MCF5307_CS_CSCR0 (*(vuint16 *)(void *)(&__MBAR[0x008A]))
#define MCF5307_CS_CSAR1 (*(vuint16 *)(void *)(&__MBAR[0x008C]))
#define MCF5307_CS_CSMR1 (*(vuint32 *)(void *)(&__MBAR[0x0090]))
#define MCF5307_CS_CSCR1 (*(vuint16 *)(void *)(&__MBAR[0x0096]))
#define MCF5307_CS_CSBAR (*(vuint8 *)(void *)(&__MBAR[0x0098]))
#define MCF5307_CS_CSBMR (*(vuint8 *)(void *)(&__MBAR[0x009C]))
#define MCF5307_CS_CSMR2 (*(vuint16 *)(void *)(&__MBAR[0x009E]))
#define MCF5307_CS_CSCR2 (*(vuint16 *)(void *)(&__MBAR[0x00A2]))
#define MCF5307_CS_CSMR3 (*(vuint16 *)(void *)(&__MBAR[0x00AA]))
#define MCF5307_CS_CSCR3 (*(vuint16 *)(void *)(&__MBAR[0x00AE]))
#define MCF5307_CS_CSMR4 (*(vuint16 *)(void *)(&__MBAR[0x00B6]))
#define MCF5307_CS_CSCR4 (*(vuint16 *)(void *)(&__MBAR[0x00BA]))
#define MCF5307_CS_CSMR5 (*(vuint16 *)(void *)(&__MBAR[0x00C2]))
#define MCF5307_CS_CSCR5 (*(vuint16 *)(void *)(&__MBAR[0x00C6]))
#define MCF5307_CS_CSMR6 (*(vuint16 *)(void *)(&__MBAR[0x00CE]))
#define MCF5307_CS_CSCR6 (*(vuint16 *)(void *)(&__MBAR[0x00D2]))
#define MCF5307_CS_CSMR7 (*(vuint16 *)(void *)(&__MBAR[0x00DA]))
#define MCF5307_CS_CSCR7 (*(vuint16 *)(void *)(&__MBAR[0x00DE]))
#endif
/* Bit level definitions and macros */
#define MCF5307_CS_CSMR_MASK_4G (0xFFFF0000)
#define MCF5307_CS_CSMR_MASK_2G (0x7FFF0000)
#define MCF5307_CS_CSMR_MASK_1G (0x3FFF0000)
#define MCF5307_CS_CSMR_MASK_1024M (0x3FFF0000)
#define MCF5307_CS_CSMR_MASK_512M (0x1FFF0000)
#define MCF5307_CS_CSMR_MASK_256M (0x0FFF0000)
#define MCF5307_CS_CSMR_MASK_128M (0x07FF0000)
#define MCF5307_CS_CSMR_MASK_64M (0x03FF0000)
#define MCF5307_CS_CSMR_MASK_32M (0x01FF0000)
#define MCF5307_CS_CSMR_MASK_16M (0x00FF0000)
#define MCF5307_CS_CSMR_MASK_8M (0x007F0000)
#define MCF5307_CS_CSMR_MASK_4M (0x003F0000)
#define MCF5307_CS_CSMR_MASK_2M (0x001F0000)
#define MCF5307_CS_CSMR_MASK_1M (0x000F0000)
#define MCF5307_CS_CSMR_MASK_1024K (0x000F0000)
#define MCF5307_CS_CSMR_MASK_512K (0x00070000)
#define MCF5307_CS_CSMR_MASK_256K (0x00030000)
#define MCF5307_CS_CSMR_MASK_128K (0x00010000)
#define MCF5307_CS_CSMR_MASK_64K (0x00000000)
#define MCF5307_CS_CSMR_CPU (0x00000020)
#define MCF5307_CS_CSAR(a) (uint16)(((a)&0xFFFF0000)>>16)
#define MCF5307_CS_CSBARx(a) (uint8)(((a)&0xFF000000)>>24)
#define MCF5307_CS_CSMR_WP (0x00000100)
#define MCF5307_CS_CSMR_AM (0x00000040)
#define MCF5307_CS_CSMR_SC (0x00000010)
#define MCF5307_CS_CSMR_SD (0x00000008)
#define MCF5307_CS_CSMR_UC (0x00000004)
#define MCF5307_CS_CSMR_UD (0x00000002)
#define MCF5307_CS_CSMR_V (0x00000001)
#define MCF5307_CS_CSCR_WS(a) (((a)&0x0F)<<10)
#define MCF5307_CS_CSCR_AA (0x0100)
#define MCF5307_CS_CSCR_PS_8 (0x0040)
#define MCF5307_CS_CSCR_PS_16 (0x0080)
#define MCF5307_CS_CSCR_PS_32 (0x0000)
#define MCF5307_CS_CSCR_BEM (0x0020)
#define MCF5307_CS_CSCR_BSTR (0x0010)
#define MCF5307_CS_CSCR_BSTW (0x0008)
/**********************************************************************/
/* Parallel Port (General Purpose I/O) Module, PP */
/**********************************************************************/
/* Read/Write access macros for general use */
#define MCF5307_PP_PADDR (*(vuint16 *)(void *)(&__MBAR[0x0244]))
#define MCF5307_PP_PADAT (*(vuint16 *)(void *)(&__MBAR[0x0248]))
/* Bit level definitions and macros */
#define MCF5307_PP_PADDR_15 (0x8000)
#define MCF5307_PP_PADDR_14 (0x4000)
#define MCF5307_PP_PADDR_13 (0x2000)
#define MCF5307_PP_PADDR_12 (0x1000)
#define MCF5307_PP_PADDR_11 (0x0800)
#define MCF5307_PP_PADDR_10 (0x0400)
#define MCF5307_PP_PADDR_9 (0x0200)
#define MCF5307_PP_PADDR_8 (0x0100)
#define MCF5307_PP_PADDR_7 (0x0080)
#define MCF5307_PP_PADDR_6 (0x0040)
#define MCF5307_PP_PADDR_5 (0x0020)
#define MCF5307_PP_PADDR_4 (0x0010)
#define MCF5307_PP_PADDR_3 (0x0008)
#define MCF5307_PP_PADDR_2 (0x0004)
#define MCF5307_PP_PADDR_1 (0x0002)
#define MCF5307_PP_PADDR_0 (0x0001)
#define MCF5307_PP_PADAT_15 (0x8000)
#define MCF5307_PP_PADAT_14 (0x4000)
#define MCF5307_PP_PADAT_13 (0x2000)
#define MCF5307_PP_PADAT_12 (0x1000)
#define MCF5307_PP_PADAT_11 (0x0800)
#define MCF5307_PP_PADAT_10 (0x0400)
#define MCF5307_PP_PADAT_9 (0x0200)
#define MCF5307_PP_PADAT_8 (0x0100)
#define MCF5307_PP_PADAT_7 (0x0080)
#define MCF5307_PP_PADAT_6 (0x0040)
#define MCF5307_PP_PADAT_5 (0x0020)
#define MCF5307_PP_PADAT_4 (0x0010)
#define MCF5307_PP_PADAT_3 (0x0008)
#define MCF5307_PP_PADAT_2 (0x0004)
#define MCF5307_PP_PADAT_1 (0x0002)
#define MCF5307_PP_PADAT_0 (0x0001)
/**********************************************************************/
/* DRAM Controller Module, DRAMC */
/**********************************************************************/
/* Read/Write access macros for general use */
#define MCF5307_DRAMC_DCR (*(vuint16 *)(void *)(&__MBAR[0x0100]))
#define MCF5307_DRAMC_DACR0 (*(vuint32 *)(void *)(&__MBAR[0x0108]))
#define MCF5307_DRAMC_DMR0 (*(vuint32 *)(void *)(&__MBAR[0x010C]))
#define MCF5307_DRAMC_DACR1 (*(vuint32 *)(void *)(&__MBAR[0x0110]))
#define MCF5307_DRAMC_DMR1 (*(vuint32 *)(void *)(&__MBAR[0x0114]))
/* Bit level definitions and macros */
#define MCF5307_DRAMC_DCR_SO (0x8000)
#define MCF5307_DRAMC_DCR_NAM (0x2000)
#define MCF5307_DRAMC_DCR_RC(a) ((a)&0x01FF)
#define MCF5307_DRAMC_DACR_BASE(a) ((a)&0xFFFC0000)
#define MCF5307_DRAMC_DACR_RE (0x00008000)
#define MCF5307_DRAMC_DACR_PS_32 (0x00000000)
#define MCF5307_DRAMC_DACR_PS_8 (0x00000010)
#define MCF5307_DRAMC_DACR_PS_16 (0x00000020)
#define MCF5307_DRAMC_DCMR_MASK_4G (0xFFFC0000)
#define MCF5307_DRAMC_DCMR_MASK_2G (0x7FFC0000)
#define MCF5307_DRAMC_DCMR_MASK_1G (0x3FFC0000)
#define MCF5307_DRAMC_DCMR_MASK_1024M (0x3FFC0000)
#define MCF5307_DRAMC_DCMR_MASK_512M (0x1FFC0000)
#define MCF5307_DRAMC_DCMR_MASK_256M (0x0FFC0000)
#define MCF5307_DRAMC_DCMR_MASK_128M (0x07FC0000)
#define MCF5307_DRAMC_DCMR_MASK_64M (0x03FC0000)
#define MCF5307_DRAMC_DCMR_MASK_32M (0x01FC0000)
#define MCF5307_DRAMC_DCMR_MASK_16M (0x00FC0000)
#define MCF5307_DRAMC_DCMR_MASK_8M (0x007C0000)
#define MCF5307_DRAMC_DCMR_MASK_4M (0x003C0000)
#define MCF5307_DRAMC_DCMR_MASK_2M (0x001C0000)
#define MCF5307_DRAMC_DCMR_MASK_1M (0x000C0000)
#define MCF5307_DRAMC_DCMR_MASK_1024K (0x00040000)
#define MCF5307_DRAMC_DCMR_MASK_512K (0x00000000)
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