mk48t02.h

motorola自己开发的针对coldfire 5272的Dbug bootloader程序

/*
 * File:		dev/mk48t02.h
 * Purpose:		Header file for MK48T02 Timekeeper and Nvram.
 *
 * Notes:		The first 2040 bytes is battery-backed nvram.
 *
 * Author:		Eric DeVolder
 * Date:
 *
 * Modifications:
 *
 */

#ifndef _DEV_MK48T02_H
#define _DEV_MK48T02_H

/********************************************************************/

#ifndef MK48T02_CUSTOM

/*
 * This macros defines the interval between registers on the device.
 */
#ifndef MK48T02_INTERVAL
#error "Must define value for MK48T02_INTERVAL"
#endif

/*
 * This macros defines the offset from zero of the first register on
 * the device.  It is then assumed that the next register is INTERVAL
 * bytes away.
 */
#ifndef MK48T02_OFFSET
#error "Must define value for MK48T02_OFFSET"
#endif

#endif /* MK48T02_CUSTOM */

/********************************************************************/
/*
 * Physical device register offsets
 */
#define MK48T02_CCR	2040	/* control	*/
#define MK48T02_CSR	2041	/* seconds	*/
#define MK48T02_CMR	2042	/* minutes	*/
#define MK48T02_CHR	2043	/* hours	*/
#define MK48T02_CDR	2044	/* day		*/
#define MK48T02_CTR	2045	/* date		*/
#define MK48T02_COR	2046	/* month	*/
#define MK48T02_CYR	2047	/* year		*/

/*
 * Definitions of register contents
 */
#define MK48T02_CCR_W		(0x80)
#define MK48T02_CCR_R		(0x40)
#define MK48T02_CCR_NORMAL	(0x00)

#define MK48T02_CSR_OSC		(0x80)
#define MK48T02_CSR_MASK	(0x7F)

#define MK48T02_CMR_MASK	(0x7F)

#define MK48T02_CHR_MASK	(0x3F)

#define MK48T02_CDR_FT		(0x40)
#define MK48T02_CDR_MASK	(0x07)

#define MK48T02_CTR_MASK	(0x3F)

#define MK48T02_COR_MASK	(0x1F)

#define MK48T02_CYR_MASK	(0xFF)

/********************************************************************/

/*
 * If the device is connected to the system in a "non-standard" way,
 * then obtain the board-specifics.
 */
#ifdef MK48T02_CUSTOM
#include MK48T02_CUSTOM	/* Local MK48T02 definitions */
#else

/*
 * Macros for accessing the peripheral registers
 */
#define Mk48t02_addr(BASE,REG)	\
	((void *)&((uint8 *)BASE)[(((int)REG) * MK48T02_INTERVAL) + MK48T02_OFFSET])

#define Mk48t02_iord(BASE,REG)      \
	cpu_iord_8(Mk48t02_addr(BASE,REG))

#define Mk48t02_iowr(BASE,REG,DATA)  \
	cpu_iowr_8(Mk48t02_addr(BASE,REG),DATA)

#define MK48T02_RD_NVRAM(BASE,CELL)			Mk48t02_iord(BASE,CELL)
#define MK48T02_WR_NVRAM(BASE,CELL,DATA)	Mk48t02_iowr(BASE,CELL,DATA)

#define MK48T02_RD_CCR(BASE)		Mk48t02_iord(BASE,MK48T02_CCR)
#define MK48T02_RD_CCR(BASE)		Mk48t02_iord(BASE,MK48T02_CCR)
#define MK48T02_RD_CSR(BASE)		Mk48t02_iord(BASE,MK48T02_CSR)
#define MK48T02_RD_CMR(BASE)		Mk48t02_iord(BASE,MK48T02_CMR)
#define MK48T02_RD_CHR(BASE)		Mk48t02_iord(BASE,MK48T02_CHR)
#define MK48T02_RD_CDR(BASE)		Mk48t02_iord(BASE,MK48T02_CDR)
#define MK48T02_RD_CTR(BASE)		Mk48t02_iord(BASE,MK48T02_CTR)
#define MK48T02_RD_COR(BASE)		Mk48t02_iord(BASE,MK48T02_COR)
#define MK48T02_RD_CYR(BASE)		Mk48t02_iord(BASE,MK48T02_CYR)

#define MK48T02_WR_CCR(BASE,DATA)	Mk48t02_iowr(BASE,MK48T02_CCR,DATA)
#define MK48T02_WR_CSR(BASE,DATA)	Mk48t02_iowr(BASE,MK48T02_CSR,DATA)
#define MK48T02_WR_CMR(BASE,DATA)	Mk48t02_iowr(BASE,MK48T02_CMR,DATA)
#define MK48T02_WR_CHR(BASE,DATA)	Mk48t02_iowr(BASE,MK48T02_CHR,DATA)
#define MK48T02_WR_CDR(BASE,DATA)	Mk48t02_iowr(BASE,MK48T02_CDR,DATA)
#define MK48T02_WR_CTR(BASE,DATA)	Mk48t02_iowr(BASE,MK48T02_CTR,DATA)
#define MK48T02_WR_COR(BASE,DATA)	Mk48t02_iowr(BASE,MK48T02_COR,DATA)
#define MK48T02_WR_CYR(BASE,DATA)	Mk48t02_iowr(BASE,MK48T02_CYR,DATA)

#endif /* MK48T02_CUSTOM */

/*
 * Fake out a typedef with void, ie MK48T02 * == void *
 */
#define MK48T02 void

/********************************************************************/

#endif /* _DEV_MK48T02_H */