lan91c111.h

motorola自己开发的针对coldfire 5272的Dbug bootloader程序

/* Pointer Register Bit Definitions */
#define	LAN91C111_PTR_RCV					0x0080 // 1=Receive area, 0=Transmit area
#define	LAN91C111_PTR_AUTOINC				0x0040 // Auto increment the pointer on each access
#define LAN91C111_PTR_READ					0x0020 // When 1 the operation is a read
#define LAN91C111_PTR_NOT_EMPTY				0x0008 // When 1 the operation is a read

/************************************************************************************************************/
/* BANK 2 - Data Register */
/* BigEndian OK */
#define LAN91C111_DATA						(*(vuint16 *)(void *)(&__ETHERNET[0x08]))
#define LAN91C111_DATA_HIGH					(*(vuint8  *)(void *)(&__ETHERNET[0x08]))
#define LAN91C111_DATA_LOW					(*(vuint8  *)(void *)(&__ETHERNET[0x09]))
/************************************************************************************************************/
/* BANK 2 Interrupt Status/Acknowledge Register */
/* BigEndian OK */
#define LAN91C111_ISR						(*(vuint16 *)(void *)(&__ETHERNET[0x0C]))

/* Interrupt Status Register Bit Definitions */
#define	LAN91C111_ISR_MDINT					0x8000 // PHY MI Register 18 Interrupt
#define	LAN91C111_ISR_ERCV_INT				0x4000 // Early Receive Interrupt
#define	LAN91C111_ISR_EPH_INT				0x2000 // Set by Etheret Protocol Handler section
#define	LAN91C111_ISR_RX_OVRN_INT			0x1000 // Set by Receiver Overruns
#define	LAN91C111_ISR_ALLOC_INT				0x0800 // Set when allocation request is completed
#define	LAN91C111_ISR_TX_EMPTY_INT			0x0400 // Set if the TX FIFO goes empty
#define	LAN91C111_ISR_TX_INT				0x0200 // Transmit Interrrupt
#define LAN91C111_ISR_RCV_INT				0x0100 // Receive Interrupt

/************************************************************************************************************/
/* BANK 2 - Interrupt Mask Register */
/* Don't konw if this is Big Endian ok???? */
#define LAN91C111_IMR						(*(vuint16  *)(void *)(&__ETHERNET[0x0C]))

/* Interrupt Mask Register Bit Definitions */
#define	LAN91C111_IMR_MDINT					0x0080 // PHY MI Register 18 Interrupt
#define	LAN91C111_IMR_ERCV_INT				0x0040 // Early Receive Interrupt
#define	LAN91C111_IMR_EPH_INT				0x0020 // Set by Etheret Protocol Handler section
#define	LAN91C111_IMR_RX_OVRN_INT			0x0010 // Set by Receiver Overruns
#define	LAN91C111_IMR_ALLOC_INT				0x0008 // Set when allocation request is completed
#define	LAN91C111_IMR_TX_EMPTY_INT			0x0004 // Set if the TX FIFO goes empty
#define	LAN91C111_IMR_TX_INT				0x0002 // Transmit Interrrupt
#define LAN91C111_IMR_RCV_INT				0x0001 // Receive Interrupt

#define	LAN91C111_IMR_ALL					(LAN91C111_IMR_MDINT|LAN91C111_IMR_ERCV_INT|LAN91C111_IMR_EPH_INT|LAN91C111_IMR_RX_OVRN_INT|LAN91C111_IMR_ALLOC_INT|LAN91C111_IMR_TX_EMPTY_INT|LAN91C111_IMR_TX_INT|LAN91C111_IMR_RCV_INT)
#define	LAN91C111_IMR_NONE					0x00


/************************************************************************************************************/
/* BANK 3 - Multicast Table Registers */
#define LAN91C111_MTR01						(*(vuint16  *)(void *)(&__ETHERNET[0x00]))
#define LAN91C111_MTR23						(*(vuint16  *)(void *)(&__ETHERNET[0x02]))
#define LAN91C111_MTR45						(*(vuint16  *)(void *)(&__ETHERNET[0x04]))
#define LAN91C111_MTR67						(*(vuint16  *)(void *)(&__ETHERNET[0x06]))

/************************************************************************************************************/
/* BANK 3 - Management Interface Register (MII) */
/* BigEndian OK */
#define LAN91C111_MII						(*(vuint16  *)(void *)(&__ETHERNET[0x08]))

/* Management Interface Register (MII) Bit Definitions */
#define LAN91C111_MII_MSK_CRS100			0x0040 // Disables CRS100 detection during tx half dup
#define LAN91C111_MII_MDOE					0x0800 // MII Output Enable
#define LAN91C111_MII_MCLK					0x0400 // MII Clock, pin MDCLK
#define LAN91C111_MII_MDI					0x0200 // MII Input, pin MDI
#define LAN91C111_MII_MDO					0x0100 // MII Output, pin MDO

/************************************************************************************************************/
/* BANK 3 - Revision Register */
/* BigEndian OK */
#define	LAN91C111_REV						(*(vuint16  *)(void *)(&__ETHERNET[0x0A])) /* ( hi: chip id   low: rev # ) */

/************************************************************************************************************/
/* BANK 3 - Early RCV Register */
/* BigEndian OK */
#define LAN91C111_ERCVR						(*(vuint16  *)(void *)(&__ETHERNET[0x0C]))

/* Early RCV Register Bit Definitions */
#define LAN91C111_ERCVR_RCV_DISCRD			0x8000 // When 1 discards a packet being received
#define LAN91C111_ERCVR_THRESHOLD			0x1F00 // ERCV Threshold Mask

/************************************************************************************************************/
/* BANK 7 - External Register */
#define	LAN91C111_EXTR						(*(vuint16  *)(void *)(&__ETHERNET[0x00]))

/************************************************************************************************************/

/* 
 . Transmit status bits 
*/
#define TS_SUCCESS 0x0100
#define TS_LOSTCAR 0x0004
#define TS_LATCOL  0x0002
#define TS_16COL   0x1000

/*
 . Receive status bits
*/
#define RS_ALGNERR		0x0080
#define RS_BRODCAST		0x0040
#define RS_BADCRC		0x0020
#define RS_ODDFRAME		0x0010	// bug: the LAN91C111 never sets this on receive
#define RS_TOOLONG		0x0008
#define RS_TOOSHORT		0x0004
#define RS_MULTICAST	0x0001
#define RS_ERRORS		(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 


// PHY Register Addresses (LAN91C111 Internal PHY)

// PHY Control Register
#define PHY_CNTL_REG		0x00
#define PHY_CNTL_RST		0x8000	// 1=PHY Reset
#define PHY_CNTL_LPBK		0x4000	// 1=PHY Loopback
#define PHY_CNTL_SPEED		0x2000	// 1=100Mbps, 0=10Mpbs
#define PHY_CNTL_ANEG_EN	0x1000 // 1=Enable Auto negotiation
#define PHY_CNTL_PDN		0x0800	// 1=PHY Power Down mode
#define PHY_CNTL_MII_DIS	0x0400	// 1=MII 4 bit interface disabled
#define PHY_CNTL_ANEG_RST	0x0200 // 1=Reset Auto negotiate
#define PHY_CNTL_DPLX		0x0100	// 1=Full Duplex, 0=Half Duplex
#define PHY_CNTL_COLTST		0x0080	// 1= MII Colision Test

// PHY Status Register
#define PHY_STAT_REG		0x01
#define PHY_STAT_CAP_T4		0x8000	// 1=100Base-T4 capable
#define PHY_STAT_CAP_TXF	0x4000	// 1=100Base-X full duplex capable
#define PHY_STAT_CAP_TXH	0x2000	// 1=100Base-X half duplex capable
#define PHY_STAT_CAP_TF		0x1000	// 1=10Mbps full duplex capable
#define PHY_STAT_CAP_TH		0x0800	// 1=10Mbps half duplex capable
#define PHY_STAT_CAP_SUPR	0x0040	// 1=recv mgmt frames with not preamble
#define PHY_STAT_ANEG_ACK	0x0020	// 1=ANEG has completed
#define PHY_STAT_REM_FLT	0x0010	// 1=Remote Fault detected
#define PHY_STAT_CAP_ANEG	0x0008	// 1=Auto negotiate capable
#define PHY_STAT_LINK		0x0004	// 1=valid link
#define PHY_STAT_JAB		0x0002	// 1=10Mbps jabber condition
#define PHY_STAT_EXREG		0x0001	// 1=extended registers implemented

// PHY Identifier Registers
#define PHY_ID1_REG			0x02	// PHY Identifier 1
#define PHY_ID2_REG			0x03	// PHY Identifier 2

// PHY Auto-Negotiation Advertisement Register
#define PHY_AD_REG			0x04
#define PHY_AD_NP			0x8000	// 1=PHY requests exchange of Next Page
#define PHY_AD_ACK			0x4000	// 1=got link code word from remote
#define PHY_AD_RF			0x2000	// 1=advertise remote fault
#define PHY_AD_T4			0x0200	// 1=PHY is capable of 100Base-T4
#define PHY_AD_TX_FDX		0x0100	// 1=PHY is capable of 100Base-TX FDPLX
#define PHY_AD_TX_HDX		0x0080	// 1=PHY is capable of 100Base-TX HDPLX
#define PHY_AD_10_FDX		0x0040	// 1=PHY is capable of 10Base-T FDPLX
#define PHY_AD_10_HDX		0x0020	// 1=PHY is capable of 10Base-T HDPLX
#define PHY_AD_CSMA			0x0001	// 1=PHY is capable of 802.3 CMSA

// PHY Auto-negotiation Remote End Capability Register
#define PHY_RMT_REG			0x05
// Uses same bit definitions as PHY_AD_REG

// PHY Configuration Register 1
#define PHY_CFG1_REG		0x10
#define PHY_CFG1_LNKDIS		0x8000	// 1=Rx Link Detect Function disabled
#define PHY_CFG1_XMTDIS		0x4000	// 1=TP Transmitter Disabled
#define PHY_CFG1_XMTPDN		0x2000	// 1=TP Transmitter Powered Down
#define PHY_CFG1_BYPSCR		0x0400	// 1=Bypass scrambler/descrambler
#define PHY_CFG1_UNSCDS		0x0200	// 1=Unscramble Idle Reception Disable
#define PHY_CFG1_EQLZR		0x0100	// 1=Rx Equalizer Disabled
#define PHY_CFG1_CABLE		0x0080	// 1=STP(150ohm), 0=UTP(100ohm)
#define PHY_CFG1_RLVL0		0x0040	// 1=Rx Squelch level reduced by 4.5db
#define PHY_CFG1_TLVL_SHIFT	2	// Transmit Output Level Adjust
#define PHY_CFG1_TLVL_MASK	0x003C
#define PHY_CFG1_TRF_MASK	0x0003	// Transmitter Rise/Fall time


// PHY Configuration Register 2
#define PHY_CFG2_REG		0x11
#define PHY_CFG2_APOLDIS	0x0020	// 1=Auto Polarity Correction disabled
#define PHY_CFG2_JABDIS		0x0010	// 1=Jabber disabled
#define PHY_CFG2_MREG		0x0008	// 1=Multiple register access (MII mgt)
#define PHY_CFG2_INTMDIO	0x0004	// 1=Interrupt signaled with MDIO pulseo

// PHY Status Output (and Interrupt status) Register
#define PHY_INT_REG			0x12	// Status Output (Interrupt Status)
#define PHY_INT_INT			0x8000	// 1=bits have changed since last read
#define	PHY_INT_LNKFAIL		0x4000	// 1=Link Not detected
#define PHY_INT_LOSSSYNC	0x2000	// 1=Descrambler has lost sync
#define PHY_INT_CWRD		0x1000	// 1=Invalid 4B5B code detected on rx
#define PHY_INT_SSD			0x0800	// 1=No Start Of Stream detected on rx
#define PHY_INT_ESD			0x0400	// 1=No End Of Stream detected on rx
#define PHY_INT_RPOL		0x0200	// 1=Reverse Polarity detected
#define PHY_INT_JAB			0x0100	// 1=Jabber detected
#define PHY_INT_SPDDET		0x0080	// 1=100Base-TX mode, 0=10Base-T mode
#define PHY_INT_DPLXDET		0x0040	// 1=Device in Full Duplex

// PHY Interrupt/Status Mask Register
#define PHY_MASK_REG		0x13	// Interrupt Mask
// Uses the same bit definitions as PHY_INT_REG



/*-------------------------------------------------------------------------
 .  I define some macros to make it easier to do somewhat common
 . or slightly complicated, repeated tasks. 
 --------------------------------------------------------------------------*/

/* select a register bank, 0 to 3  */
/* #define SMC_SELECT_BANK(x)  { outw( x, ioaddr + BANK_SELECT ); }  */

#define SMC_SELECT_BANK(x)			LAN91C111_BSR = (x<<8)

/* this enables an interrupt in the interrupt mask register 
#define SMC_ENABLE_INT(x) {\
		unsigned char mask;\
		SMC_SELECT_BANK(2);\
		mask = inb( ioaddr + IM_REG );\
		mask |= (x);\
		outb( mask, ioaddr + IM_REG ); \
}
*/
/* this disables an interrupt from the interrupt mask register 

#define SMC_DISABLE_INT(x) {\
		unsigned char mask;\
		SMC_SELECT_BANK(2);\
		mask = inb( ioaddr + IM_REG );\
		mask &= ~(x);\
		outb( mask, ioaddr + IM_REG ); \
}*/

/*----------------------------------------------------------------------
 . Define the interrupts that I want to receive from the card
 . 
 . I want: 
 .  IM_EPH_INT, for nasty errors
 .  IM_RCV_INT, for happy received packets
 .  IM_RX_OVRN_INT, because I have to kick the receiver
 .  IM_MDINT, for PHY Register 18 Status Changes
 --------------------------------------------------------------------------
#define SMC_INTERRUPT_MASK   (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
	IM_MDINT) 

*/
 
#endif  /* _LAN91C111_H_ */