ns16550a.h

motorola自己开发的针对coldfire 5272的Dbug bootloader程序

/*
 * File:		ns16550a.h
 * Purpose:		Definition for the NS16550 UART.
 *
 * Notes:
 *
 * Author:		Eric DeVolder	[e-mail]
 * Date:		2-19-96
 *
 * Modifications:
 *
 */

typedef volatile struct
{
	BYTE	BR;
	/* DLAB = 0: BR = Receive Buffer (read)  Transmit Holding (write) */
	/* DLAB = 1: BR = Divisor Latch Least Significant Byte (write)    */
	BYTE	IER;
	/* DLAB = 0: IER = Interrupt Enable Register (read and write) */
	/* DLAB = 1: IER = Divisor Latch Most Significant Byte (write)    */
	BYTE	IIR;		/* Interrupt ID (read) FIFO Control (write) */
	BYTE	LCR;		/* Line control (read and write) */
	BYTE	MCR;		/* Modem Control Register (read and write) */
	BYTE	LSR;		/* Line Status Control Register (read and write) */
	BYTE	MSR;		/* Modem Status Register (read and write) */
	BYTE	SCR;		/* Scratch pad register */
} NS16550A;


/*
 * Definitions for the various registers in the NS16550A.
 */

/* Interrupt Enable Register, IER */
#define IER_ERBFI		(0x01)
#define IER_ETBEI		(0x02)
#define IER_ELSI		(0x04)
#define IER_EDSSI		(0x08)

/* Interrupt Identification Register, IIR (read only) */
#define IIR_INT_PENDING_MASK	(0x01)
#define IIR_INT_IDENT_MASK		(0x0E)
#define IIR_FIFO_ENABLED		(0xC0)

/* FIFO Control Register, FCR (write only) */
#define FCR_FIFO_ENABLE			(0x01)
#define FCR_RCVR_FIFO_RESET		(0x02)
#define FCR_XMIT_FIFO_RESET		(0x04)
#define	FCR_DMA_MODE_SELECT		(0x10)
#define FCR_RCVR_TRIGGER_01		(0x00)
#define FCR_RCVR_TRIGGER_04		(0x40)
#define FCR_RCVR_TRIGGER_08		(0x80)
#define FCR_RCVR_TRIGGER_14		(0xC0)

/* Line Control Register, LCR */
#define LCR_WLS0				(0x01)
#define LCR_WLS1				(0x02)
#define LCR_STOP_BIT			(0x04)
#define LCR_PARITY_ENABLE		(0x08)
#define LCR_EPS					(0x10)
#define LCR_STICKY_PARITY		(0x20)
#define LCR_SET_BREAK			(0x40)
#define LCR_DLAB				(0x80)

/* Common communications configurations */
#define EIGHT_DATA_NO_PARITY_ONE_STOP	\
	(LCR_WLS0 | LCR_WLS1)

#define SEVEN_DATA_EVEN_PARITY_ONE_STOP	\
	(LCR_WLS1 | LCR_PARITY_ENABLE | LCR_EPS)

/* Modem Control Register, MCR */
#define MCR_DTR					(0x01)
#define MCR_RTS					(0x02)
#define MCR_OUT1				(0x04)
#define MCR_OUT2				(0x08)
#define MCR_LOOP				(0x10)

/* Line Status Register, LSR */
#define LSR_DATA_READY			(0x01)
#define LSR_OVERRUN_ERR			(0x02)
#define LSR_PARITY_ERR			(0x04)
#define LSR_FRAME_ERR			(0x08)
#define LSR_BREAK_INTERRUPT		(0x10)
#define LSR_THR_EMPTY			(0x20)
#define LSR_TX_EMPTY			(0x40)
#define LSR_FIFO_RCVR_ERR		(0x80)

/* MODEM Status Register, MSR */
#define MSR_DCTS				(0x01)
#define MSR_DDSR				(0x02)
#define MSR_TERI				(0x04)
#define MSR_DDCD				(0x08)
#define MSR_CTS					(0x10)
#define MSR_DSR					(0x20)
#define MSR_RI					(0x40)
#define MSR_DCD					(0x80)

/* Divisor Latch Values -- depend upon input oscillator frequency */


#if (defined(OSC_1_843MHZ))
#define BPS_1200	(96)
#define BPS_2400	(48)
#define BPS_9600	(12)
#define BPS_19200	(6)
#define BPS_38400	(3)
#endif

#if (defined(OSC_3_072MHZ))
#define BPS_1200	(160)
#define BPS_2400	(80)
#define BPS_9600	(20)
#define BPS_19200	(10)
#define BPS_38400	(5)
#endif

#if (defined(OSC_3_686MHZ))
#define BPS_1200	(192)
#define BPS_2400	(96)
#define BPS_9600	(24)
#define BPS_19200	(12)
#define BPS_38400	(6)
#endif

#if (defined(OSC_8_000MHZ))
#define BPS_1200	(417)
#define BPS_2400	(208)
#define BPS_9600	(52)
#define BPS_19200	(26)
#define BPS_38400	(13)
#endif

#if (defined(OSC_18_432MHZ))
#define BPS_1200	(960)
#define BPS_2400	(480)
#define BPS_9600	(120)
#define BPS_19200	(60)
#define BPS_38400	(30)
#endif

void
ns16550a_init (NS16550A *, int);

int
ns16550a_in_char (NS16550A *);

void
ns16550a_out_char (NS16550A *, int);

int
ns16550a_char_present (NS16550A *);