gmd_internal.h

motorola自己开发的针对coldfire 5272的Dbug bootloader程序

/***************  gmd_internal.h  ********************************************

FUNCTION: Internal definitions for Motorola GMD drivers

 VERSION: 2000.12.05 Chuck Kuecker (www.RickMiller.com)
          2001.02.02 Rick Miller <www.RickMiller.com> added censor stuff
          2001.02.11 Rick Miller    increased shadow size
          2001.02.12 Rick Miller    added C3F_NO_CENSORSHIP1,2
          2001.02.13 Rick Miller    removed incorrect FLASHID
          2001.10.29 Jiazheng Shi   updated to fit MPC56x with C3F
          2001.11.07 Emily Liu      included module numbers for MPC56x with C3F
   NOTES:
     USE:
*/

#ifndef GMD_INTERNAL
#define GMD_INTERNAL

/****** Macro for GMD functions and demos *********************/
#define WORD_SIZE                          4
#define C3F_MAX_MODULES					   2
#define C3F_MODULES_MPC565				   2
#define C3F_MODULES_MPC563				   1

#define BLOCKS_IN_MODULE_A                 8
#define C3F_MODULE_SIZE                    0x80000
#define C3F_SHADOW_SIZE                    0x200
#define BLOCK_SIZE                         (C3F_MODULE_SIZE / BLOCKS_IN_MODULE_A)
#define MODULE_A_SIZE                      (BLOCKS_IN_MODULE_A * BLOCK_SIZE)
#define C3F_CLEARED_CENSORSHIP             0
#define C3F_NO_CENSORSHIP1                 1
#define C3F_NO_CENSORSHIP2                 2
#define C3F_INFORMATION_CENSORSHIP         3
#define DEVICE_CENSORED                    0
#define DEVICE_UNCENSORED                  1

/****** Register access definitions ************************/
#define IMMR_ISB_MASK                      0x0000000E
#define IMMR_FLEN_MASK                     0x00000800
#define IMMR_PARTNUM_MASK                  0xFF000000
#define MPC561_PARTNUM                     0x35000000
#define MPC562_PARTNUM                     0x01000000
#define MPC563_PARTNUM                     0x36000000
#define MPC564_PARTNUM                     0x02000000
#define MPC565_PARTNUM                     0x33000000
#define MPC566_PARTNUM                     0x03000000

#define C3F_ADDR                           0x002FC800   // C3F register base address
#define C3F_ADDR_OFFSET                    0x00000040   // offset between A&B register addresses

#define C3F_MODULE_A                       0
#define C3F_MODULE_B                       1

#define C3FMCR_A_ADDR                      C3F_ADDR     // these addresses are added to any IMMR offsets.
#define C3FMCR_B_ADDR                      (C3F_ADDR + C3F_ADDR_OFFSET)

#define C3FMCRE_A_ADDR                     (C3F_ADDR + 4)
#define C3FMCRE_B_ADDR                     (C3F_ADDR + C3F_ADDR_OFFSET +4)

#define C3FCTL_A_ADDR                      (C3F_ADDR + 8)
#define C3FCTL_B_ADDR                      (C3F_ADDR + C3F_ADDR_OFFSET +8)

#define C3FMCR_STOP_MASK                   0x80000000
#define C3FMCR_LOCK_MASK                   0x40000000
#define C3FMCR_FIC_MASK                    0x10000000
#define C3FMCR_ACCESS_MASK                 0x04000000
#define C3FMCR_SIE_MASK                    0x08000000
#define C3FMCR_CENSOR_MASK                 0x03000000
#define C3FMCR_SUPV_MASK                   0x00FF0000
#define C3FMCR_DATA_MASK                   0x0000FF00
#define C3FMCR_PROTECT_MASK                0x000000FF

#define C3FMCRE_SBEN_MASK                  0xC0000000
#define C3FMCRE_SBSUPV_MASK                0x30000000
#define C3FMCRE_SBDATA_MASK                0x0C000000
#define C3FMCRE_SBPROTECT_MASK             0x03000000
#define C3FMCRE_FLASHID_MASK               0x000000FF

#define C3FCTL_HVS_MASK                    0x80000000
#define C3FCTL_PEGOOD_MASK                 0x40000000
#define C3FCTL_PEFI_MASK                   0x20000000
#define C3FCTL_EPEE_MASK                   0x10000000
#define C3FCTL_BOEPEE_MASK                 0x08000000
#define C3FCTL_SBBLOCK_MASK                0x00030000
#define C3FCTL_BLOCK_MASK                  0x0000FF00
#define C3FCTL_CSC_MASK                    0x00000040
#define C3FCTL_HSUS_MASK                   0x00000008
#define C3FCTL_PE_MASK                     0x00000004
#define C3FCTL_SES_MASK                    0x00000002
#define C3FCTL_EHV_MASK                    0x00000001

/****************************************************************************/
/*                              MODULE :C3F                                 */
/****************************************************************************/
struct C3F_tag {
    struct {                /*C3F EEPROM Configuration Register*/
        VUINT32 STOP:1;
        VUINT32 LOCK:1;
        VUINT32 BPB:1;
        VUINT32 FIC:1;
        VUINT32 SIE:1;
        VUINT32 ACCESS:1;
        VUINT32 CENSOR:2;
        VUINT32 SUPV:8;
        VUINT32 DATA:8;
        VUINT32 PROTECT:8;
    } C3FMCR;
    struct {                /*C3F EEPROM Extended Configuration Register*/
        VUINT32 SBEN:2;
        VUINT32 SBSUPV:2;
        VUINT32 SBDATA:2;
        VUINT32 SBPROTECT:2;
        VUINT32 WAIT:2;
        VUINT32 GPBIU:6;
        VUINT32 MEMSIZ:3;
        VUINT32 BLK:1;
        VUINT32 MAP:1;
        VUINT32 SBLKL:2;
        VUINT32 FLASHID:9;
    } C3FMCRE;
    struct {                /*C3F EEPROM High Voltage Control Register*/
        VUINT32 HVS:1;
        VUINT32 PEGOOD:1;
        VUINT32 PEFI:1;
        VUINT32 EPEE:1;
        VUINT32 BOEM:1;
        VUINT32:9;
        VUINT32 SBBLOCK:2;
        VUINT32 BLOCK:8;
        VUINT32:1;
        VUINT32 CSC:1;
        VUINT32:2;
        VUINT32 HSUS:1;
        VUINT32 PE:1;
        VUINT32 SES:1;
        VUINT32 EHV:1;
    } C3FCTL;
};

#endif

/* End of gmd_internal.h */