📄 brgs.h
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/*
* File: brgs.h
* Purpose: Definitions of various baud rate generator divisors
*
* Notes: div = (BRGCLK / (16 * BAUD)) - 1 <-- assumes no div16
*
* Author: Eric DeVolder
* Date:
*
* Modifications:
*
*/
/********************************************************************/
/*
* BRGCLK of 3.375 MHz
*/
#define MPC8XX_BRG_3_375MHZ_9600BPS_DIVIDER (21<<1) /* 20.97 */
#define MPC8XX_BRG_3_375MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_3_375MHZ_19200BPS_DIVIDER (10<<1) /* 9.99 */
#define MPC8XX_BRG_3_375MHZ_19200BPS_DIV16 (0x00000000)
/*
* BRGCLK of 6.75 MHz
*/
#define MPC8XX_BRG_6_75MHZ_9600BPS_DIVIDER (43<<1) /* 42.94 */
#define MPC8XX_BRG_6_75MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_6_75MHZ_19200BPS_DIVIDER (21<<1) /* 20.97 */
#define MPC8XX_BRG_6_75MHZ_19200BPS_DIV16 (0x00000000)
/*
* BRGCLK of 12.5 MHz
*/
#define MPC8XX_BRG_12_5MHZ_9600BPS_DIVIDER (80<<1) /* 80.38 */
#define MPC8XX_BRG_12_5MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_12_5MHZ_19200BPS_DIVIDER (39<<1) /* 39.69 */
#define MPC8XX_BRG_12_5MHZ_19200BPS_DIV16 (0x00000000)
/*
* BRGCLK of 12 MHz
*/
#define MPC8XX_BRG_12MHZ_9600BPS_DIVIDER (77<<1) /* 77.13 */
#define MPC8XX_BRG_12MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_12MHZ_19200BPS_DIVIDER (38<<1) /* 38.56 */
#define MPC8XX_BRG_12MHZ_19200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_12MHZ_38400BPS_DIVIDER (19<<1) /* 19.28 */
#define MPC8XX_BRG_12MHZ_38400BPS_DIV16 (0x00000000)
/*
* BRGCLK of 13.5 MHz
*/
#define MPC8XX_BRG_13_5MHZ_1200BPS_DIVIDER (702<<1) /* 702.125 */
#define MPC8XX_BRG_13_5MHZ_1200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_13_5MHZ_9600BPS_DIVIDER (86<<1) /* 86.89 */
#define MPC8XX_BRG_13_5MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_13_5MHZ_19200BPS_DIVIDER (43<<1) /* 42.94 */
#define MPC8XX_BRG_13_5MHZ_19200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_13_5MHZ_38400BPS_DIVIDER (21<<1) /* 21.47 */
#define MPC8XX_BRG_13_5MHZ_38400BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_13_5MHZ_115000BPS_DIVIDER (6<<1) /* 6.33 */
#define MPC8XX_BRG_13_5MHZ_115000BPS_DIV16 (0x00000000)
/*
* BRGCLK of 27 MHz
*/
#define MPC8XX_BRG_27MHZ_1200BPS_DIVIDER (1404<<1) /* 1404.25 */
#define MPC8XX_BRG_27MHZ_1200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_27MHZ_4800BPS_DIVIDER (87<<1) /* 87.89 */
#define MPC8XX_BRG_27MHZ_4800BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_27MHZ_9600BPS_DIVIDER (173<<1) /* 173.78 */
#define MPC8XX_BRG_27MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_27MHZ_19200BPS_DIVIDER (85<<1) /* 85.88 */
#define MPC8XX_BRG_27MHZ_19200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_27MHZ_38400BPS_DIVIDER (43<<1) /* 43.44 */
#define MPC8XX_BRG_27MHZ_38400BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_27MHZ_115000BPS_DIVIDER (14<<1) /* 13.67 */
#define MPC8XX_BRG_27MHZ_115000BPS_DIV16 (0x00000000)
/*
* BRGCLK of 20 MHz
*/
#define MPC8XX_BRG_20MHZ_50BPS_DIVIDER (1561<<1)
#define MPC8XX_BRG_20MHZ_50BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_20MHZ_75BPS_DIVIDER (1040<<1)
#define MPC8XX_BRG_20MHZ_75BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_20MHZ_150BPS_DIVIDER (520<<1)
#define MPC8XX_BRG_20MHZ_150BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_20MHZ_300BPS_DIVIDER (259<<1)
#define MPC8XX_BRG_20MHZ_300BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_20MHZ_600BPS_DIVIDER (2082<<1)
#define MPC8XX_BRG_20MHZ_600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_20MHZ_1200BPS_DIVIDER (1040<<1)
#define MPC8XX_BRG_20MHZ_1200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_20MHZ_2400BPS_DIVIDER (520<<1)
#define MPC8XX_BRG_20MHZ_2400BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_20MHZ_4800BPS_DIVIDER (259<<1)
#define MPC8XX_BRG_20MHZ_4800BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_20MHZ_9600BPS_DIVIDER (129<<1)
#define MPC8XX_BRG_20MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_20MHZ_19200BPS_DIVIDER (64<<1)
#define MPC8XX_BRG_20MHZ_19200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_20MHZ_38400BPS_DIVIDER (32<<1)
#define MPC8XX_BRG_20MHZ_38400BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_20MHZ_57600BPS_DIVIDER (21<<1)
#define MPC8XX_BRG_20MHZ_57600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_20MHZ_115200BPS_DIVIDER (10<<1)
#define MPC8XX_BRG_20MHZ_115200BPS_DIV16 (0x00000000)
/*
* BRGCLK of 24 MHz
*/
#define MPC8XX_BRG_24MHZ_50BPS_DIVIDER (1919<<1)
#define MPC8XX_BRG_24MHZ_50BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_24MHZ_75BPS_DIVIDER (1279<<1)
#define MPC8XX_BRG_24MHZ_75BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_24MHZ_150BPS_DIVIDER (639<<1)
#define MPC8XX_BRG_24MHZ_150BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_24MHZ_300BPS_DIVIDER (319<<1)
#define MPC8XX_BRG_24MHZ_300BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_24MHZ_600BPS_DIVIDER (2559<<1)
#define MPC8XX_BRG_24MHZ_600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_24MHZ_1200BPS_DIVIDER (1279<<1)
#define MPC8XX_BRG_24MHZ_1200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_24MHZ_2400BPS_DIVIDER (639<<1)
#define MPC8XX_BRG_24MHZ_2400BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_24MHZ_4800BPS_DIVIDER (319<<1)
#define MPC8XX_BRG_24MHZ_4800BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_24MHZ_9600BPS_DIVIDER (159<<1)
#define MPC8XX_BRG_24MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_24MHZ_19200BPS_DIVIDER (79<<1)
#define MPC8XX_BRG_24MHZ_19200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_24MHZ_38400BPS_DIVIDER (39<<1)
#define MPC8XX_BRG_24MHZ_38400BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_24MHZ_57600BPS_DIVIDER (26<<1)
#define MPC8XX_BRG_24MHZ_57600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_24MHZ_115200BPS_DIVIDER (12<<1)
#define MPC8XX_BRG_24MHZ_115200BPS_DIV16 (0x00000000)
/*
* BRGCLK of 25 MHz
*/
#define MPC8XX_BRG_25MHZ_50BPS_DIVIDER (1952<<1)
#define MPC8XX_BRG_25MHZ_50BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_25MHZ_75BPS_DIVIDER (1301<<1)
#define MPC8XX_BRG_25MHZ_75BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_25MHZ_150BPS_DIVIDER (650<<1)
#define MPC8XX_BRG_25MHZ_150BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_25MHZ_300BPS_DIVIDER (324<<1)
#define MPC8XX_BRG_25MHZ_300BPS_DIV16 (0x00000001)
#define MPC8XX_BRG_25MHZ_600BPS_DIVIDER (2603<<1)
#define MPC8XX_BRG_25MHZ_600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_25MHZ_1200BPS_DIVIDER (1301<<1)
#define MPC8XX_BRG_25MHZ_1200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_25MHZ_2400BPS_DIVIDER (650<<1)
#define MPC8XX_BRG_25MHZ_2400BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_25MHZ_4800BPS_DIVIDER (324<<1)
#define MPC8XX_BRG_25MHZ_4800BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_25MHZ_9600BPS_DIVIDER (162<<1)
#define MPC8XX_BRG_25MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_25MHZ_19200BPS_DIVIDER (80<<1)
#define MPC8XX_BRG_25MHZ_19200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_25MHZ_38400BPS_DIVIDER (40<<1)
#define MPC8XX_BRG_25MHZ_38400BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_25MHZ_57600BPS_DIVIDER (26<<1)
#define MPC8XX_BRG_25MHZ_57600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_25MHZ_115200BPS_DIVIDER (13<<1)
#define MPC8XX_BRG_25MHZ_115200BPS_DIV16 (0x00000000)
/*
* BRGCLK of 32 MHz
*/
#define MPC8XX_BRG_32MHZ_19200BPS_DIVIDER (103<<1)
#define MPC8XX_BRG_32MHZ_19200BPS_DIV16 (0x00000000)
/*
* BRGCLK of 50 MHz
*/
#define MPC8XX_BRG_50MHZ_9600BPS_DIVIDER (325<<1) /* 324.52 */
#define MPC8XX_BRG_50MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_50MHZ_19200BPS_DIVIDER (161<<1) /* 161.7 */
#define MPC8XX_BRG_50MHZ_19200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_50MHZ_38400BPS_DIVIDER (81<<1)
#define MPC8XX_BRG_50MHZ_38400BPS_DIV16 (0x00000000)
/*
* BRGCLK of 54 MHz
*/
#define MPC8XX_BRG_54MHZ_9600BPS_DIVIDER (350<<1) /* 350.56 */
#define MPC8XX_BRG_54MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_54MHZ_19200BPS_DIVIDER (174<<1) /* 174.8 */
#define MPC8XX_BRG_54MHZ_19200BPS_DIV16 (0x00000000)
/*
* BRGCLK when System Frequency is 54MHZ and CLOCKS.SCCR[DFBRG] = 4
*/
#define MPC8XX_BRG_13_5MHZ_4800BPS_DIVIDER (175<<1) /* 175.78 */
#define MPC8XX_BRG_13_5MHZ_4800BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_13_5MHZ_9600BPS_DIVIDER (86<<1) /* 86.89 */
#define MPC8XX_BRG_13_5MHZ_9600BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_13_5MHZ_19200BPS_DIVIDER (43<<1) /* 42.94 */
#define MPC8XX_BRG_13_5MHZ_19200BPS_DIV16 (0x00000000)
#define MPC8XX_BRG_13_5MHZ_38400BPS_DIVIDER (21<<1) /* 21.47 */
#define MPC8XX_BRG_13_5MHZ_38400BPS_DIV16 (0x00000000)
/********************************************************************/
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