sysinit.c

motorola自己开发的针对coldfire 5272的Dbug bootloader程序

/*
 * File:		sysinit.c
 * Purpose:		Power-on Reset configuration of the MCF5272.
 *
 * Notes:
 *
 * Author:		Michael Norman
 * Date:		
 *
 */

#include "src/include/dbug.h"

/********************************************************************/

void mcf5272_sim_init(void);
void mcf5272_gpio_init(void);
void mcf5272_cs_init(void);
void mcf5272_sdram_init(void);
void mcf5272_uart_init(void);

/********************************************************************/
void
mcf5272_init(void)
{
	mcf5272_uart_init();
	mcf5272_sim_init();
	mcf5272_gpio_init();
	mcf5272_cs_init();
	mcf5272_sdram_init();
}

/****************************************************************/
void
mcf5272_sim_init(void)
{
	/*
	 * Initialize System Config Register
	 * Setup Watch Dog Timeout
	 */
	MCF5272_SIM_SCR = MCF5272_SIM_SCR_HWWD_1024;

	/*
	 * Initialize System Protection Register
	 * Enable all bus error exceptions
	 */
	MCF5272_SIM_SPR = (0
		| MCF5272_SIM_SPR_ADC | MCF5272_SIM_SPR_ADCEN
		| MCF5272_SIM_SPR_WPV | MCF5272_SIM_SPR_WPVEN
		| MCF5272_SIM_SPR_SMV | MCF5272_SIM_SPR_SMVEN
		| MCF5272_SIM_SPR_SBE | MCF5272_SIM_SPR_SBEEN
		| MCF5272_SIM_SPR_HWT | MCF5272_SIM_SPR_HWTEN
		| MCF5272_SIM_SPR_RPV | MCF5272_SIM_SPR_RPVEN
		| MCF5272_SIM_SPR_EXT | MCF5272_SIM_SPR_EXTEN
		| MCF5272_SIM_SPR_SUV | MCF5272_SIM_SPR_SUVEN
		) ;

	/* 
	 * Initilize Interrupt Control Registers
	 * Mask all interrupt sources
	 */
	MCF5272_SIM_ICR1 = 0x88888888;
	MCF5272_SIM_ICR2 = 0x88888888;
	MCF5272_SIM_ICR3 = 0x88888888;
	MCF5272_SIM_ICR4 = 0x88880000;

	/* 
	 * Initialize Programmable Interrupt Transition Register
	 * Make all external interrupts trigger on falling edge
	 */	
	MCF5272_SIM_PITR = MCF5272_SIM_PITR_NEG_EDGE;

	/*
	 * Initialize Programmable Interrupt Vector Register
	 * Place peripheral interrupt vectors beginning at vector 64
	 */
	MCF5272_SIM_PIVR = MCF5272_SIM_PIVR_NORMAL;
}
/********************************************************************/
void 
mcf5272_gpio_init(void)
{
	/* Inititialize Port A */

	/* Enable USB signals */
	MCF5272_GPIO_PACNT = 0x00001555;
	/* Configure all pins as inputs */
	MCF5272_GPIO_PADDR = 0;

	/* Inititialize Port B */

	/* Enable UART0 and FEC signals*/
	MCF5272_GPIO_PBCNT = 0x55554155;
	/* Configure all GPIO pins as inputs */
	MCF5272_GPIO_PBDDR = 0;
	
	/* Inititialize Port D */
	
	/* Enable UART1 signals */
	MCF5272_GPIO_PDCNT = 0x000002A8;
}

/********************************************************************/
void
mcf5272_uart_init(void)
{
	register uint16 ubgs;

	/* Reset Transmitter */
	MCF5272_UART0_UCR = MCF5272_UART_UCR_RESET_TX;
	MCF5272_UART1_UCR = MCF5272_UART_UCR_RESET_TX;

	/* Reset Receiver */
	MCF5272_UART0_UCR = MCF5272_UART_UCR_RESET_RX;
	MCF5272_UART1_UCR = MCF5272_UART_UCR_RESET_RX;

	/* Reset Mode Register */
	MCF5272_UART0_UCR = MCF5272_UART_UCR_RESET_MR;
	MCF5272_UART1_UCR = MCF5272_UART_UCR_RESET_MR;

	/* No parity, 8-bits per character */
	MCF5272_UART0_UMR = (0
		| MCF5272_UART_UMR1_PM_NONE
		| MCF5272_UART_UMR1_BC_8 );
	MCF5272_UART1_UMR = (0
		| MCF5272_UART_UMR1_PM_NONE
		| MCF5272_UART_UMR1_BC_8 );

	/* No echo or loopback, 1 stop bit */
	MCF5272_UART0_UMR = (0
		| MCF5272_UART_UMR2_CM_NORMAL
		| MCF5272_UART_UMR2_STOP_BITS_1);
	MCF5272_UART1_UMR = (0
		| MCF5272_UART_UMR2_CM_NORMAL
		| MCF5272_UART_UMR2_STOP_BITS_1);

	/* Set Rx and Tx baud by timer */
	MCF5272_UART0_UCSR = (0
		| MCF5272_UART_UCSR_RCS(0xD)
		| MCF5272_UART_UCSR_TCS(0xD));
	MCF5272_UART1_UCSR = (0
		| MCF5272_UART_UCSR_RCS(0xD)
		| MCF5272_UART_UCSR_TCS(0xD));

	/* Mask all UART interrupts */
	MCF5272_UART0_UIMR = 0;
	MCF5272_UART1_UIMR = 0;
                 
	/* Calculate baud settings */
	ubgs = (uint16)((SYSTEM_CLOCK*1000000)/(board_get_baud() * 32));

	MCF5272_UART0_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
	MCF5272_UART0_UBG2 = (uint8)(ubgs & 0x00FF);
	MCF5272_UART1_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
	MCF5272_UART1_UBG2 = (uint8)(ubgs & 0x00FF);

	/* Enable receiver and transmitter */
	MCF5272_UART0_UCR = (0
		| MCF5272_UART_UCR_TX_ENABLED
		| MCF5272_UART_UCR_RX_ENABLED);
	MCF5272_UART1_UCR = (0
		| MCF5272_UART_UCR_TX_ENABLED
		| MCF5272_UART_UCR_RX_ENABLED);
}
/********************************************************************/
void
mcf5272_sdram_init(void)
{
	/* Do not initialize SDRAM if it is already active */
	if (!(MCF5272_SDRAMC_SDCCR & MCF5272_SDRAMC_SDCCR_ACT))
	{
		switch (SYSTEM_CLOCK)
		{
			case 48:
				MCF5272_SDRAMC_SDCTR = (0
					| MCF5272_SDRAMC_SDCTR_RTP_48MHz
					| MCF5272_SDRAMC_SDCTR_RC(0)
					| MCF5272_SDRAMC_SDCTR_RP(1)
					| MCF5272_SDRAMC_SDCTR_RCD(0)
					| MCF5272_SDRAMC_SDCTR_CLT_2);
				break;
			case 33:
				MCF5272_SDRAMC_SDCTR = (0
					| MCF5272_SDRAMC_SDCTR_RTP_33MHz
					| MCF5272_SDRAMC_SDCTR_RC(0)
					| MCF5272_SDRAMC_SDCTR_RP(0)
					| MCF5272_SDRAMC_SDCTR_RCD(0)
					| MCF5272_SDRAMC_SDCTR_CLT_2);
				break;
			case 25:
				MCF5272_SDRAMC_SDCTR = (0
					| MCF5272_SDRAMC_SDCTR_RTP_25MHz
					| MCF5272_SDRAMC_SDCTR_RC(0)
					| MCF5272_SDRAMC_SDCTR_RP(0)
					| MCF5272_SDRAMC_SDCTR_RCD(0)
					| MCF5272_SDRAMC_SDCTR_CLT_2);
				break;
			case 66:
			default:
				MCF5272_SDRAMC_SDCTR = (0
					| MCF5272_SDRAMC_SDCTR_RTP_66MHz
					| MCF5272_SDRAMC_SDCTR_RC(0)
					| MCF5272_SDRAMC_SDCTR_RP(1)
					| MCF5272_SDRAMC_SDCTR_RCD(1)
					| MCF5272_SDRAMC_SDCTR_CLT_2);
				break;
		}
		
		MCF5272_SDRAMC_SDCCR = (0
			| MCF5272_SDRAMC_SDCCR_MCAS_A9
#if defined(M5272C3_PRE_R22)
			| MCF5272_SDRAMC_SDCCR_BALOC_A21
#else
			| MCF5272_SDRAMC_SDCCR_BALOC_A22
#endif
			| MCF5272_SDRAMC_SDCCR_REG
			| MCF5272_SDRAMC_SDCCR_INIT);
	}
}
/********************************************************************/
void
mcf5272_cs_init(void)
{
	/* This routine initializes ChipSelects to setup memory devices */

	/* ChipSelect 0 - 2MB FLASH */
	MCF5272_CS_CSBR0 = (0
		| MCF5272_CS_BR_BASE(FLASH_ADDRESS)
		| MCF5272_CS_BR_SRAM
		| MCF5272_CS_BR_PS_16
		| MCF5272_CS_BR_EN);	
	MCF5272_CS_CSOR0 = (0
		| MCF5272_CS_OR_MASK_2M
		| MCF5272_CS_OR_WS(5));

	/* Chip Select 2 - 512KB SRAM */
	MCF5272_CS_CSBR2 = (0
		| MCF5272_CS_BR_BASE(EXT_SRAM_ADDRESS)
		| MCF5272_CS_BR_SRAM
		| MCF5272_CS_BR_PS_32
		| MCF5272_CS_BR_EN);
	MCF5272_CS_CSOR2 = (0
		| MCF5272_CS_OR_MASK_512K
		| MCF5272_CS_OR_WS(0));

	/* ChipSelect 7 - 4MB or 16MB SDRAM */
	MCF5272_CS_CSBR7 = (0
		| MCF5272_CS_BR_BASE(SDRAM_ADDRESS)
		| MCF5272_CS_BR_SDRAM 
		| MCF5272_CS_BR_PS_LINE 
		| MCF5272_CS_BR_EN);
	MCF5272_CS_CSOR7 = (0
#if defined(M5272C3_PRE_R22)
		| MCF5272_CS_OR_MASK_4M
#else
		| MCF5272_CS_OR_MASK_16M
#endif
		| MCF5272_CS_OR_WS(0x1F));
}

/********************************************************************/