board.c

针对freescale的coldfire系列mcu的开源bootloader源码colilo的优化代码

#include "arch.h"
#include "mcfuart.h"
//
// 2003.01.05 IAFG
//   The engtech.ca board is based on the Arcturus UCDIMM.
//   the intention is to get FOPIS working first, then take what it learned and create an ARcturus UCDIMM vendor as well.
//
// Revisions:
// 2002.12.20 KT - Initial hack for Arcturus UCDIMM by 
// 2003.01.05 IAFG - Review and document. 
//  - appears that setupDRAM():MCFSIM_SDTR value is set for 66Mhz clock(0xf539) should be 0xAC39 for 48Mhz.
//  - note: setupboard():MCFSIM_PACNT=0x00000000 Port A control register setting doesn't enable UART1. 
//     (Don't believe this makes any difference at this point.)

//char	ident[] = "Arcturus UCDIMM";		//Initial changes by Ken for UCDIMM
char	ident[] = "Engtech.ca FOPIS";		//
char	copyright[] = "(C) 2002 Ken Treis, Iain Galloway";

extern unsigned int downloadPort;
extern unsigned int image_size;
extern unsigned char *xfer_addr;
extern unsigned char *down_addr;
extern unsigned char *dest_addr;
extern unsigned char *source_addr;

extern unsigned long consoleBase;

void configureConsole()
{
	consoleBase = MCFUART_BASE1;
	configureSerial(consoleBase, 19200, 48000000);
}

void configureAuxSerial() {}

void setLED() {}

void setImageParams()
{
	downloadPort = 0;		// Sets which serial port to use for download
	image_size = 0x001e0000;		// Compressed Image Size
	source_addr = (unsigned char *)0x10c10000;	// Compressed Image is at this address
	down_addr = (unsigned char *)0x10c10000;	// Download image to this address
	xfer_addr = (unsigned char *)0x20000;	// Transfer Address to start execution at
	dest_addr = (unsigned char *)0x20000;	// Decompress image to this address
}
 
void setupBoard()
{
	volatile unsigned char	*mbar;
	mbar = (volatile unsigned char *) MCF_MBAR;

	// stuff that was added for dbug compliance (sim_init)
	mbar_writeShort(MCFSIM_SCR, 0x0003);	//SysConfigReg: Hardware watchdog HWR(1024clk) = 3
	mbar_writeShort(MCFSIM_SPR, 0xFFFF);	//SysProtectionReg: Enable all bus cycle error sources.
	mbar_writeLong(MCFSIM_ICR1, 0x88888888);//Interrupt control reg(s),
	mbar_writeLong(MCFSIM_ICR2, 0x88888888);//  set pending bit, and(but?) disable
	mbar_writeLong(MCFSIM_ICR3, 0x88888888);
	mbar_writeLong(MCFSIM_ICR4, 0x88880000);
	mbar_writeLong(MCFSIM_PITR, 0x00000000);//Programmable Interrupt Transition Reg.
	mbar_writeByte(MCFSIM_PIVR, 0x00000040);//programmable Interrupt Vector Reg.

	mbar_writeLong(MCFSIM_PACNT, 0x00000000);//PortA_Control: Set all Pins as PortA i/o
	// more stuff from dbug (gpio_init)
	mbar_writeShort(MCFSIM_PADDR, 0x0000);	//PortA Data Dir: 0 = All in.
	mbar_writeLong(MCFSIM_PBCNT, 0x55554155);//PortB Control: allows the console to work
	mbar_writeShort(MCFSIM_PBDDR, 0x0000);	//PortB Data Dir: 0 = All in
	mbar_writeLong(MCFSIM_PDCNT, 0x00000000);//PortD Control: (NOTE!! No UART1 pins enabled.)

	// CS0: FLASH
	// 
	//   CSBRx "Chip seslect Base Register"
	//   0x10C00... = Base Address
	//   0x.....2.. = Bus width: (0b10 = 16bits)
	//   0x.......1 = Enable this CS
	//   
	//   CSOrx "CS Option Register"
	//   0xFFC00... = BAM (Address mask)
	//   0x......14 = 0b.00101.. + 0b......00
	//              =       WS   +        RW+MRW
	//              =     WS=0x05+        Memory is read/write
	//
	mbar_writeLong(MCFSIM_CSBR0, 0x10c00201); //Base Address = 0x10C00xxx
	mbar_writeLong(MCFSIM_CSOR0, 0xFFC00014); //Match = 0x10Cxxx

	// CS7: SDRAM
	// Match = 0x007xxxxx, SDRAM = 0x400, Cache Line = 0x300, Enable = 1
	mbar_writeLong(MCFSIM_CSBR7, 0x00000601); //Base Address = 0x00000xxx
	mbar_writeLong(MCFSIM_CSOR7, 0xFF80017C); //Match 0x007xxx. WS(0x1F) = External, burst mode
	
	// CS1, CS2, CS3, CS4, CS5, and CS6 are unused on the UCDIMM.
	mbar_writeLong(MCFSIM_CSBR1, 0);
	mbar_writeLong(MCFSIM_CSOR1, 0);
	mbar_writeLong(MCFSIM_CSBR2, 0);
	mbar_writeLong(MCFSIM_CSOR2, 0);
	mbar_writeLong(MCFSIM_CSBR3, 0);
	mbar_writeLong(MCFSIM_CSOR3, 0);
	mbar_writeLong(MCFSIM_CSBR4, 0);
	mbar_writeLong(MCFSIM_CSOR4, 0);
	mbar_writeLong(MCFSIM_CSBR5, 0);
	mbar_writeLong(MCFSIM_CSOR5, 0);
	mbar_writeLong(MCFSIM_CSBR6, 0);
	mbar_writeLong(MCFSIM_CSOR6, 0);
}

void setupDRAM()
{
	// Notes added by IAFG for Engtech.ca FOPIS board.
	volatile unsigned char *mbar = (unsigned char *)MCF_MBAR;
	
	//mbar_writeLong(MCFSIM_SDTR, 0xF539); //RTP = 0xF5 for 66mhz
	mbar_writeLong(MCFSIM_SDTR, 0xAC39); //RTP should be 0xAC for 48Mhz 

	//mbar_writeLong(MCFSIM_SDCR, 0x4211);
	mbar_writeLong(MCFSIM_SDCR, 0x2211); //MCAS should be 0x2
	// For Micron chip MT48LC4M16A2 (1Meg x 16 x4 banks) Maximum column addressing
	// is 256 (A0-A7), but since the MCF5272 is configured as 16bit external
	// bus, A7 of the SDRAM connects to A8 of the MCF5272.
	// Therefore MCAS = 0b01, MSB = 0b0010 = 0x2
	//
	// BALOC is determined from the table in the Motorola users manual 
	// (MCF5272UM/D) "Internal address multiplexing (16 bit address bus).
	// For a 64 Mbit part, and 16 bit address bus, SDBA0 = A22, SDBA1 = A23.
	// For this requirement, BALOC = 0b010, MSBByte-1 = 0b0010 = 0x2 
	
	// Dummy write to start SDRAM
	*((volatile unsigned long *)0) = 0;
}