board.c

针对freescale的coldfire系列mcu的开源bootloader源码colilo的优化代码

/*
 * Copyright 2002 (C) Ken Treis; Key Technology, Inc.
 * [e-mail]
 */
#include "arch.h"
#include "mcfuart.h"

char	ident[] = "Key Technology 701335";
char	copyright[] = "(C) 2002 Key Technology, Inc.";

extern unsigned int downloadPort;
extern unsigned int image_size;
extern unsigned char *xfer_addr;
extern unsigned char *down_addr;
extern unsigned char *dest_addr;
extern unsigned char *source_addr;

extern unsigned int consoleBase;

void configureConsole()
{
	consoleBase = MCFUART_BASE2;
	configureSerial(consoleBase, 19200, 60000000);
}

void configureAuxSerial() {}

void setLED(int state) {}

void setImageParams()
{
	downloadPort = 1;
	image_size = 0x001c0000;
	source_addr = (unsigned char *)0xf0010000;
	down_addr = (unsigned char *)0xf0010000;
	xfer_addr = (unsigned char *)0x20000;
	dest_addr = (unsigned char *)0x20000;
}

void setupBoard()
{
	volatile unsigned char	*mbar;
	mbar = (volatile unsigned char *) MCF_MBAR;

	// stuff that was added for dbug compliance (sim_init)
	mbar_writeShort(MCFSIM_SCR, 0x0003);
	mbar_writeShort(MCFSIM_SPR, 0xFFFF);
	mbar_writeLong(MCFSIM_ICR1, 0x88888888);
	mbar_writeLong(MCFSIM_ICR2, 0x88888888);
	mbar_writeLong(MCFSIM_ICR3, 0x88888888);
	mbar_writeLong(MCFSIM_ICR4, 0x88880000);
	mbar_writeLong(MCFSIM_PITR, 0x00000000);
	mbar_writeByte(MCFSIM_PIVR, 0x00000040);

	mbar_writeLong(MCFSIM_PACNT, 0x00000000);
	mbar_writeLong(MCFSIM_PBCNT, 0x55550000);	// Enable Ethernet 
	mbar_writeLong(MCFSIM_PDCNT, 0x000002aa);	// Set port D for second UART

	// init chip-selects to setup memory devices
	//
	//
	// CSBR -- chip select base register
	//
	//  xxxx xxxx xxxx xxxx xxxx 0000 0000 0000
	//                         . .... .... ...+ - enable
	//                         . .... .... ..+ -- compare TM (no)
	//                         . .... ...+ ++ --- transfer modifier (reserved)
	//                         . .... .++ ------- transfer type
	//                         . .... + --------- supervisor mode (no)
	//                         . ..++ ----------- bus width (long word)
	//                         . ++ ------------- ebi (SDRAM)
	//  ++++++++++++++++++++++++ ---------------- base addr
	// (8-3)
	//
	//
	// CSOR -- chip select option register
	//
	//  xxxx xxxx xxxx xxxx xxxx 0000 x000 0000
	//                         . .... .... ...+ - MRW, enable/disable RW
	//                         . .... .... ..+ -- RW
	//                         . .... .+++ ++ --- wait state generator
	//                         . .... +---------- reserved
	//                         . ...+ ----------- EXTBURST
	//                         . ..+ ------------ RDAH, enable/disable addr & attribute
	//                         . .+ ------------- WRAH, enable/disable addr hold
	//                         . + -------------- address setup and enable
	//  ++++++++++++++++++++++++ ---------------- base addr MASK
	//
	
	// CS0: FLASH, mapped at 0xF0000000
	// Bus width is 16, 5 wait states
	//
	//  xxxx xxxx xxxx xxxx xxxx 0010 0000 0001 CSBR
	//  xxxx xxxx xxxx xxxx xxxx 0000 0001 0100 CSOR
	//
	mbar_writeLong(MCFSIM_CSBR0, 0xF0000201);
	mbar_writeLong(MCFSIM_CSOR0, 0xFFC00014);

	// CS1: Link Layer Control, mapped at 0x40000000
	//
	//  xxxx xxxx xxxx xxxx xxxx 0010 0000 0001 CSBR
	//  xxxx xxxx xxxx xxxx xxxx 0000 0000 1100 CSOR
	//
	mbar_writeLong(MCFSIM_CSBR1, 0x40000201);
	mbar_writeLong(MCFSIM_CSOR1, 0xFFFFF00C);

	// CS2 & CS3: Seg Memory, mapped at 0x50000000 and 0x60000000
	// Bus width is 32
	//
	//  xxxx xxxx xxxx xxxx xxxx 0000 0000 0001 CSBR
	//  xxxx xxxx xxxx xxxx xxxx 1110 0111 1100 CSOR
	//
	mbar_writeLong(MCFSIM_CSBR2, 0x50000001);
	mbar_writeLong(MCFSIM_CSOR2, 0xFF800E7C);
	mbar_writeLong(MCFSIM_CSBR3, 0x60000001);
	mbar_writeLong(MCFSIM_CSOR3, 0xFF800E7C);

	// CS4: Frame Buffer, mapped at 0x70000000
	// Bus width is 32
	//
	mbar_writeLong(MCFSIM_CSBR4, 0x70000001);
	mbar_writeLong(MCFSIM_CSOR4, 0xFF800E7C);

	// CS5: Test Image, mapped at 0x80000000
	// Bus width is 32
	//
	mbar_writeLong(MCFSIM_CSBR5, 0x80000001);
	mbar_writeLong(MCFSIM_CSOR5, 0xFF800E7C);

	// CS6: FPGA, mapped at 0x90000000
	// Bus width is 32, 3 wait states
	//
	//  xxxx xxxx xxxx xxxx xxxx 0001 0000 0001 CSBR
	//  xxxx xxxx xxxx xxxx xxxx 0000 0000 1100 CSOR
	//
	mbar_writeLong(MCFSIM_CSBR6, 0x90000001);
	mbar_writeLong(MCFSIM_CSOR6, 0xFF80000C);
	
	// CS7: SDRAM, mapped at 0x00000000
	// 
	mbar_writeLong(MCFSIM_CSBR7, 0x00000701);
	mbar_writeLong(MCFSIM_CSOR7, 0xFF80007C); 
}

void setupDRAM()
{
	volatile unsigned char *mbar = (unsigned char *)MCF_MBAR;

	mbar_writeLong(MCFSIM_SDTR, 0xF539);
	mbar_writeLong(MCFSIM_SDCR, 0x4211);

	// Dummy write to start SDRAM
	*((volatile unsigned long *)0) = 0;

	// We use the PWM to provide a refresh cycle on the external
	// SDRAMs.
	//
	// PWCR -- PWM control register
	//
	//  0000 0000
	//  .... ++++ - CKSL, prescale clock
	//  ...+ ------ reserved
	//  ..+-------- LVL, disable level
	//  .+--------- FRC1, force output high
	//  +---------- EN, enable
	// (18-3)
	//
	// PWWR -- PWM pulse width register
	//
	//  0000 0000
	//  ++++ ++++ - PW, pulse width
	// (18-4)

	// For our use, the duty cycle is 50%, frequency is 8.5 uS
	//  PWCR: 1000 0001
	//  PWWR: 1000 0000
	mbar_writeByte(MCFSIM_PWWR0, 0x80);
	mbar_writeByte(MCFSIM_PWCR0, 0x81);
}