s3c2510.h

S3c2510下的VXWORKS的BSP源代码（包括了以太网、串口、USB等等驱动）

/* UART Status Register Bit Definitions */

#define S3C2510_HUSTAT_TFFUL            0x00100000          /* Transmit FIFO Full */
#define S3C2510_HUSTAT_TFEMT            0x00080000          /* Transmit FIFO Empty */
#define S3C2510_USTAT_THE               0x00040000          /* Transmit Holding Register Empty */
#define S3C2510_USTAT_TXI               0x00020000          /* Transmitter Idle */
#define S3C2510_HUSTAT_ECTS             0x00010000          /* CTS Event Occurred */
#define S3C2510_HUSTAT_CTS              0x00008000          /* Clear To Send */
#define S3C2510_HUSTAT_DSR              0x00004000          /* Data Set Ready */
#define S3C2510_HUSTAT_ERXTO            0x00001000          /* Receive Event Timeout */
#define S3C2510_USTAT_RXI               0x00000800          /* Receiver in Idle */
#define S3C2510_HUSTAT_RFOV             0x00000400          /* Receive FIFO Overrun */
#define S3C2510_HUSTAT_RFFUL            0x00000200          /* Receive FIFO Full */
#define S3C2510_HUSTAT_RFEMT            0x00000100          /* Receive FIFO Empty */
#define S3C2510_HUSTAT_RFREA            0x00000080          /* Receive FIFO Trigger Level Reached */
#define S3C2510_HUSTAT_DCD              0x00000040          /* Data Carrier Detected */
#define S3C2510_USTAT_CCD               0x00000020          /* Control Character Detected */
#define S3C2510_USTAT_OER               0x00000010          /* Overrun Error */
#define S3C2510_USTAT_PER               0x00000008          /* Parity Error */
#define S3C2510_USTAT_FER               0x00000004          /* Frame Error */
#define S3C2510_USTAT_BSD               0x00000002          /* Break Signal Detected */
#define S3C2510_USTAT_RDV               0x00000001          /* Receive Data Valid */

/* UART Interrupt Enable Register Bit Definitions */

#define S3C2510_UINT_THEIE              0x00040000          /* Transmit Holding Register Empty Interrupt Enable */
#define S3C2510_UINT_TXIIE              0x00020000          /* Transmitter Idle Interrupt Enable */
#define S3C2510_HUINT_ECTSIE            0x00010000          /* CTS Event Occurred Interrupt Enable */
#define S3C2510_HUINT_ERXTOIE           0x00001000          /* Receive Event Timeout Interrupt Enable */
#define S3C2510_HUINT_OVFFIE            0x00000400          /* Receive FIFO Overrun Interrupt Enable */
#define S3C2510_HUINT_RFREAIE           0x00000080          /* Receive FIFO Trigger Level Reached Interrupt Enable */
#define S3C2510_HUINT_DCDIE             0x00000040          /* Data Carrier Detected Interrupt Enable */
#define S3C2510_UINT_CCDIE              0x00000020          /* Control Character Detected Interrupt Enable */
#define S3C2510_UINT_OERIE              0x00000010          /* Overrun Error Interrupt Enable */
#define S3C2510_UINT_PERIE              0x00000008          /* Parity Error Interrupt Enable */
#define S3C2510_UINT_FERIE              0x00000004          /* Frame Error Interrupt Enable */
#define S3C2510_UINT_BSDIE              0x00000002          /* Break Signal Detected Interrupt Enable */
#define S3C2510_UINT_RDVIE              0x00000001          /* Receive Data Valid Interrupt Enable */

/* UART Baud Rate Divisor Register Bit Definitions */

#define S3C2510_UBRD_CNT_MASK           0x0000FFF0          /* Time Constant Value */
#define     S3C2510_UBRD_CNT_SHIFT          4
#define S3C2510_UBRD_DIVISOR_MASK       0x00000001          /* Baud Rate Divisor */
#define     S3C2510_UBRD_DIV_1              0x00000000      /* Divide by 1 */
#define     S3C2510_UBRD_DIV_16             0x00000001      /* Divide by 16 */


/*******************************************************************************
        S3C2510 DES/3DES Special Registers
*******************************************************************************/

#define S3C2510_DESCON                  REG_32(0x00090000)   /* DES/3DES Control Register */
#define S3C2510_DESSTA                  REG_32(0x00090004)   /* DES/3DES Status Register */
#define S3C2510_DESINT                  REG_32(0x00090008)   /* DES/3DES Interrupt Enable Register */
#define S3C2510_DESRUN                  REG_32(0x0009000C)   /* DES/3DES Run Enable Register */
#define S3C2510_DESKEY1L                REG_32(0x00090010)   /* DES/3DES Key 1 Left Half */
#define S3C2510_DESKEY1R                REG_32(0x00090014)   /* DES/3DES Key 1 Right Half */
#define S3C2510_DESKEY2L                REG_32(0x00090018)   /* DES/3DES Key 2 Left Half */
#define S3C2510_DESKEY2R                REG_32(0x0009001C)   /* DES/3DES Key 2 Right Half */
#define S3C2510_DESKEY3L                REG_32(0x00090020)   /* DES/3DES Key 3 Left Half */
#define S3C2510_DESKEY3R                REG_32(0x00090024)   /* DES/3DES Key 3 Right Half */
#define S3C2510_DESIVL                  REG_32(0x00090028)   /* DES/3DES IV Left Half */
#define S3C2510_DESIVR                  REG_32(0x0009002C)   /* DES/3DES IV Right Half */
#define S3C2510_DESINFIFO               REG_32(0x00090030)   /* DES/3DES Input FIFO */
#define S3C2510_DESOUTFIFO              REG_32(0x00090034)   /* DES/3DES Output FIFO */

/* DES/3DES Controlr Register Bit Definitions */

#define S3C2510_DESCON_FIFO_RESET       0x00000200          /* FIFO Reset */
#define S3C2510_DESCON_FIFO_TEST        0x00000100          /* FIFO Test */
#define S3C2510_DESCON_4WORD_REQ        0x00000000          /* DES Generate Valid DESOUTFIFO Bit when it has 4 Word Valid Data */
#define S3C2510_DESCON_2WORD_REQ        0x00000080          /* DES Generate Valid DESOUTFIFO Bit when it has 2 Word Valid Data */
#define S3C2510_DESCON_ECB              0x00000000          /* ECB */
#define S3C2510_DESCON_CBC              0x00000040          /* CBC */
#define S3C2510_DESCON_DES              0x00000000          /* DES */
#define S3C2510_DESCON_3DES             0x00000020          /* 3DES */
#define S3C2510_DESCON_MODE_MASK        0x00000010
#define S3C2510_DESCON_ENCRYPTION       0x00000000          /* Encryption */
#define S3C2510_DESCON_DECRYPTION       0x00000010          /* Decryption */
#define S3C2510_DESCON_R2L_DATA         0x00000008          /* Right Half to Left Half Data Transfer */
#define S3C2510_DESCON_OUTDATA_DMA      0x00000004          /* GDMA Transfer Output Data */
#define S3C2510_DESCON_INDATA_DMA       0x00000002          /* GDMA Transfer Input Data */
#define S3C2510_DESCON_RUN_ENABLE       0x00000001          /* DES/3DES Enable */

/* DES/3DES Status Register Bit Definitions */

#define S3C2510_DESSTA_OFIFO_FULL       0x00000400          /* Output FIFO Full */
#define S3C2510_DESSTA_OFIFO_EMPTY      0x00000200          /* Output FIFO Empty */
#define S3C2510_DESSTA_OFIFO_VALID      0x00000100          /* Output FIFO Ready */
#define S3C2510_DESSTA_IFIFO_FULL       0x00000040          /* Input FIFO Full */
#define S3C2510_DESSTA_IFIFO_EMPTY      0x00000020          /* Input FIFO Ready */
#define S3C2510_DESSTA_IFIFO_AVAIL      0x00000010          /* Input FIFO Avail */
#define S3C2510_DESSTA_IDLE             0x00000001          /* Idle */

/* DES/3DES Interrupt Enable Register Bit Definitions */

#define S3C2510_DESINT_OFIFO_VALID      0x00000100          /* Output FIFO Valid Interrupt Enable */
#define S3C2510_DESINT_IFIFO_AVAIL      0x00000010          /* Input FIFO Avail Interrupt Enable */
#define S3C2510_DESINT_IDLE             0x00000001          /* Idle Interrupt Enable */


/*******************************************************************************
        S3C2510 Ethernet Controller Special Registers
*******************************************************************************/

#define S3C2510_BTXCON(_n)              REG_32(0x000A0000 + _n * 0x20000)   /* BDMA Tx Control Register */
#define S3C2510_BRXCON(_n)              REG_32(0x000A0004 + _n * 0x20000)   /* BDMA Rx Control Register */
#define S3C2510_BTXBDPTR(_n)            REG_32(0x000A0008 + _n * 0x20000)   /* BDMA TBD Start Address Register */
#define S3C2510_BRXBDPTR(_n)            REG_32(0x000A000C + _n * 0x20000)   /* BDMA RBD Start Address Register */
#define S3C2510_BTXBDCNT(_n)            REG_32(0x000A0010 + _n * 0x20000)   /* BDMA TBD Counter Register */
#define S3C2510_BRXBDCNT(_n)            REG_32(0x000A0014 + _n * 0x20000)   /* BDMA RBD Counter Register */
#define S3C2510_BMTXINTEN(_n)           REG_32(0x000A0018 + _n * 0x20000)   /* BDMA-MAC Tx Interrupt Enable Register */
#define S3C2510_BMRXINTEN(_n)           REG_32(0x000A001C + _n * 0x20000)   /* BDMA-MAC Rx Interrupt Enable Register */
#define S3C2510_BMTXSTAT(_n)            REG_32(0x000A0020 + _n * 0x20000)   /* BDMA-MAC Tx Interrupt Status Register */
#define S3C2510_BMRXSTAT(_n)            REG_32(0x000A0024 + _n * 0x20000)   /* BDMA-MAC Rx Interrupt Status Register */
#define S3C2510_BRXLEN(_n)              REG_32(0x000A0028 + _n * 0x20000)   /* BDMA Receive Frame Size Register */

#define S3C2510_CFTXSTAT(_n)            REG_32(0x000A0030 + _n * 0x20000)   /* MAC Tx Control Frame Status Register */
#define S3C2510_MACCON(_n)              REG_32(0x000B0000 + _n * 0x20000)   /* MAC Control Register */
#define S3C2510_CAMCON(_n)              REG_32(0x000B0004 + _n * 0x20000)   /* CAM Control Register */
#define S3C2510_MTXCON(_n)              REG_32(0x000B0008 + _n * 0x20000)   /* MAC Tx Control Register */
#define S3C2510_MTXSTAT(_n)             REG_32(0x000B000C + _n * 0x20000)   /* MAC Tx Status Register */
#define S3C2510_MRXCON(_n)              REG_32(0x000B0010 + _n * 0x20000)   /* MAC Rx Control Register */
#define S3C2510_MRXSTAT(_n)             REG_32(0x000B0014 + _n * 0x20000)   /* MAC Rx Status Register */

/* We changed design, so it has one MDC, MDIO */
#define S3C2510_STADATA(_n)             REG_16(0x000B0018 + _n * 0x00000)   /* MAC Station Management Data Register */
#define S3C2510_STACON(_n)              REG_16(0x000B001C + _n * 0x00000)   /* MAC Station Management Control and Address Register */

#define S3C2510_CAMEN(_n)               REG_32(0x000B0028 + _n * 0x20000)   /* CAM Enable Register */
#define S3C2510_MISSCNT(_n)             REG_32(0x000B003C + _n * 0x20000)   /* MAC Missed Error Count Register */
#define S3C2510_PZCNT(_n)               REG_32(0x000B0040 + _n * 0x20000)   /* MAC Received Pause Count Register */
#define S3C2510_RMPZCNT(_n)             REG_32(0x000B0044 + _n * 0x20000)   /* MAC Remote Pause Count Register */
#define S3C2510_CAM(_n)                 REG_8 (0x000B0080 + _n * 0x20000)   /* CAM Register */

/* BDMA Transmit Control Register Bit Definitions */

#define S3C2510_BTXCON_RESET            0x00000800          /* BDMA Tx Block Reset */
#define S3C2510_BTXCON_EN               0x00000400          /* BDMA Tx Block Enable */
#define S3C2510_BTXCON_SL_MASK              0x00000070      /* BDMA Transmit to MAC Tx Start Level */
#define     S3C2510_BTXCON_SL_0             0x00000000      /* No Wait */
#define     S3C2510_BTXCON_SL_1             0x00000010      /* Wait to Fill 1/8 of BDMA Tx Buffer */
#define     S3C2510_BTXCON_SL_2             0x00000020      /* Wait to Fill 2/8 of BDMA Tx Buffer */
#define     S3C2510_BTXCON_SL_3             0x00000030      /* Wait to Fill 3/8 of BDMA Tx Buffer */
#define     S3C2510_BTXCON_SL_4             0x00000040      /* Wait to Fill 4/8 of BDMA Tx Buffer */
#define     S3C2510_BTXCON_SL_5             0x00000050      /* Wait to Fill 5/8 of BDMA Tx Buffer */
#define     S3C2510_BTXCON_SL_6             0x00000060      /* Wait to Fill 6/8 of BDMA Tx Buffer */
#define     S3C2510_BTXCON_SL_7             0x00000070      /* Wait to Fill 7/8 of BDMA Tx Buffer */
#define S3C2510_BTXCON_NBD_MASK         0x0000000F          /* BDMA Tx Number of Buffer Descriptor */

/* BDMA Receive Control Register Bit Definitions */

#define S3C2510_BRXCON_RESET            0x00000800          /* BDMA Rx Block Reset */
#define S3C2510_BRXCON_EN               0x00000400          /* BDMA Rx Block Enable */
#define S3C2510_BRXCON_WA_MASK          0x00000030          /* BDMA Rx Word Alignment */
#define     S3C2510_BRXCON_WA_0             0x00000000      /* No Invalid Bytes */
#define     S3C2510_BRXCON_WA_1             0x00000010      /* 1 Invalid Byte */
#define     S3C2510_BRXCON_WA_2             0x00000020      /* 2 Invalid Bytes */
#define     S3C2510_BRXCON_WA_3             0x00000030      /* 3 Invalid Bytes */
#define     S3C2510_BRXCON_WA_SHIFT         4
#define S3C2510_BRXCON_NBD_MASK         0x0000000F          /* BDMA Rx Number of Buffer Descriptor */

/* BDMA/MAC Tx Interrupt Enable Register Bit Definitions */

#define S3C2510_BMTXINTEN_BEMPTYIE      0x00040000          /* BDMA Tx Buffer Empty Interrupt Enable */
#define S3C2510_BMTXINTEN_BNOIE         0x00020000          /* BDMA Tx Not Owner Interrupt Enable */
#define S3C2510_BMTXINTEN_MTXCFCOMPIE   0x00010000          /* MAC Tx Complete to Send Control Frame Interrupt Enable */
#define S3C2510_BMTXINTEN_MCOMPIE       0x00000040          /* MAC Tx Completion Interrupt Enable */
#define S3C2510_BMTXINTEN_MPARERRIE     0x00000020          /* MAC Tx Parity Error Interrupt Enable */
#define S3C2510_BMTXINTEN_MLATECOLLIE   0x00000010          /* MAC Tx Late Collision Interrupt Enable */
#define S3C2510_BMTXINTEN_MNOCARRIE     0x00000008          /* MAC Tx No Carrier Interrupt Enable */
#define S3C2510_BMTXINTEN_MDEFERERRIE   0x00000004          /* MAC Tx Deferral Error Interrupt Enable */
#define S3C2510_BMTXINTEN_MUNFERFLOWIE  0x00000002          /* MAC Tx Underflow Interrupt Enable */
#define S3C2510_BMTXINTEN_MEXCOLLIE     0x00000001          /* MAC Tx Excessive Collision In