📄 s3c2510.h
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#define S3C2510_TCNT2 REG_32(0x00040024) /* Timer 2 Count Register */
#define S3C2510_TDATA3 REG_32(0x00040028) /* Timer 3 Data Register */
#define S3C2510_TCNT3 REG_32(0x0004002C) /* Timer 3 Count Register */
#define S3C2510_TDATA4 REG_32(0x00040030) /* Timer 4 Data Register */
#define S3C2510_TCNT4 REG_32(0x00040034) /* Timer 4 Count Register */
#define S3C2510_TDATA5 REG_32(0x00040038) /* Timer 5 Data Register */
#define S3C2510_TCNT5 REG_32(0x0004003C) /* Timer 5 Count Register */
/* Timer Mode Register Bit Definitions. */
#define S3C2510_TMOD_TCLR5 0x00400000 /* Timer 5 Initial TOUT5 Value */
#define S3C2510_TMOD_TMD5 0x00200000 /* Timer 5 Mode Selection */
#define S3C2510_TMOD_TE5 0x00100000 /* Timer 5 Enable */
#define S3C2510_TMOD_TCLR4 0x00040000 /* Timer 4 Initial TOUT4 Value */
#define S3C2510_TMOD_TMD4 0x00020000 /* Timer 4 Mode Selection */
#define S3C2510_TMOD_TE4 0x00010000 /* Timer 4 Enable */
#define S3C2510_TMOD_TCLR3 0x00004000 /* Timer 3 Initial TOUT3 Value */
#define S3C2510_TMOD_TMD3 0x00002000 /* Timer 3 Mode Selection */
#define S3C2510_TMOD_TE3 0x00001000 /* Timer 3 Enable */
#define S3C2510_TMOD_TCLR2 0x00000400 /* Timer 2 Initial TOUT2 Value */
#define S3C2510_TMOD_TMD2 0x00000200 /* Timer 2 Mode Selection */
#define S3C2510_TMOD_TE2 0x00000100 /* Timer 2 Enable */
#define S3C2510_TMOD_TCLR1 0x00000040 /* Timer 1 Initial TOUT1 Value */
#define S3C2510_TMOD_TMD1 0x00000020 /* Timer 1 Mode Selection */
#define S3C2510_TMOD_TE1 0x00000010 /* Timer 1 Enable */
#define S3C2510_TMOD_TCLR0 0x00000004 /* Timer 0 Initial TOUT0 Value */
#define S3C2510_TMOD_TMD0 0x00000002 /* Timer 0 Mode Selection */
#define S3C2510_TMOD_TE0 0x00000001 /* Timer 0 Enable */
/* Timer Interrupt Clear Register Bit Definitions */
#define S3C2510_TIC_T5 0x00000040 /* Timer 5 Interrupt Clear */
#define S3C2510_TIC_T4 0x00000020 /* Timer 4 Interrupt Clear */
#define S3C2510_TIC_T3 0x00000010 /* Timer 3 Interrupt Clear */
#define S3C2510_TIC_T2 0x00000008 /* Timer 2 Interrupt Clear */
#define S3C2510_TIC_T1 0x00000004 /* Timer 1 Interrupt Clear */
#define S3C2510_TIC_T0 0x00000002 /* Timer 0 Interrupt Clear */
#define S3C2510_TIC_WDT 0x00000001 /* Watchdog Timer Interrupt Clear */
/* Watchdog Timer Register Bit Definitions */
#define S3C2510_WDT_EN 0x80000000 /* Watchdog Timer Enable */
#define S3C2510_WDT_MODE_MASK 0x40000000 /* Watchdog Timer Mode */
#define S3C2510_WDT_MODE_INTERRUPT 0x00000000 /* Interrupt Mode */
#define S3C2510_WDT_MODE_RESET 0x40000000 /* Reset Mode */
#define S3C2510_WDT_RST 0x20000000 /* Watchdog Timer Counter Reset */
#define S3C2510_WDT_WDTVAL_MASK 0x0003FFFF /* Watchdog Timer Timeout Value */
/*******************************************************************************
S3C2510 GDMA Special Registers
*******************************************************************************/
#define S3C2510_DPRIC REG_32(0x00051000) /* GDMA Priority Configuration Register */
#define S3C2510_DPRIF REG_32(0x00052000) /* GDMA Programmable Priority Register for Fixed */
#define S3C2510_DPRIR REG_32(0x00053000) /* GDMA Programmable Priority Register for Round-Robin */
#define S3C2510_DCON(_n) REG_32(0x00050000 + _n * 0x20) /* GDMA Control Register */
#define S3C2510_DSAR(_n) REG_32(0x00050004 + _n * 0x20) /* GDMA Source Address Register */
#define S3C2510_DDAR(_n) REG_32(0x00050008 + _n * 0x20) /* GDMA Destination Address Register */
#define S3C2510_DTCR(_n) REG_32(0x0005000C + _n * 0x20) /* GDMA Trnasfer Count Register */
#define S3C2510_DRER(_n) REG_32(0x00050010 + _n * 0x20) /* GDMA Run Enable Register */
#define S3C2510_DIPR(_n) REG_32(0x00050014 + _n * 0x20) /* GDMA Interrupt Pending Register */
/* GDMA Control Register Bit Definitions */
#define S3C2510_DCON_BS 0x80000000 /* Busy Status */
#define S3C2510_DCON_XCNT_MASK 0x0001E000 /* External DMA ACK Cycle Count */
#define S3C2510_DCON_XCNT_1 0x00000000
#define S3C2510_DCON_XCNT_2 0x00002000
#define S3C2510_DCON_XCNT_3 0x00004000
#define S3C2510_DCON_XCNT_4 0x00006000
#define S3C2510_DCON_XCNT_5 0x00008000
#define S3C2510_DCON_XCNT_6 0x0000A000
#define S3C2510_DCON_XCNT_7 0x0000C000
#define S3C2510_DCON_XCNT_8 0x0000E000
#define S3C2510_DCON_XCNT_9 0x00010000
#define S3C2510_DCON_XCNT_10 0x00012000
#define S3C2510_DCON_XCNT_11 0x00014000
#define S3C2510_DCON_XCNT_12 0x00016000
#define S3C2510_DCON_XCNT_13 0x00018000
#define S3C2510_DCON_XCNT_14 0x0001A000
#define S3C2510_DCON_XCNT_15 0x0001C000
#define S3C2510_DCON_XCNT_16 0x0001E000
#define S3C2510_DCON_IE 0x00001000 /* Interrupt Enable */
#define S3C2510_DCON_DD_MASK 0x00000C00
#define S3C2510_DCON_DD_INC 0x00000000 /* Increase Destination Address */
#define S3C2510_DCON_DD_DEC 0x00000400 /* Decrease Destination Address */
#define S3C2510_DCON_DD_FIX 0x00000800 /* Do not change Destination Address */
#define S3C2510_DCON_SD_MASK 0x00000300
#define S3C2510_DCON_SD_INC 0x00000000 /* Increase Source Address */
#define S3C2510_DCON_SD_DEC 0x00000100 /* Decrease Source Address */
#define S3C2510_DCON_SD_FIX 0x00000200 /* Do not change Source Address */
#define S3C2510_DCON_TS_MASK 0x000000C0
#define S3C2510_DCON_TS_8 0x00000000 /* Transfer Size is 8 Bits */
#define S3C2510_DCON_TS_16 0x00000040 /* Transfer Size is 16 Bits */
#define S3C2510_DCON_TS_32 0x00000080 /* Transfer Size is 32 Bits */
#define S3C2510_DCON_FB 0x00000020 /* Enable 4 Data Burst Mode */
#define S3C2510_DCON_SB 0x00000010 /* Single or Block mode */
#define S3C2510_DCON_MODE_MASK 0x0000000E
#define S3C2510_DCON_MODE_SOFT 0x00000000 /* Memory to Memory */
#define S3C2510_DCON_MODE_EXTDREQ 0x00000002 /* External Device */
#define S3C2510_DCON_MODE_HUARTTX 0x00000004 /* Memory to HUART */
#define S3C2510_DCON_MODE_HUARTRX 0x00000006 /* HUART to Memory */
#define S3C2510_DCON_MODE_DESIN 0x00000008 /* Memory to DES */
#define S3C2510_DCON_MODE_DESOUT 0x0000000A /* DES to Memory */
#define S3C2510_DCON_RE 0x00000001 /* Run Enable */
/*******************************************************************************
S3C2510 UART Controller Special Registers
*******************************************************************************/
#define S3C2510_UCON(_n) REG_32(0x00060000 + _n * 0x10000) /* UART Control Register */
#define S3C2510_USTAT(_n) REG_32(0x00060004 + _n * 0x10000) /* UART Status Register */
#define S3C2510_UINT(_n) REG_32(0x00060008 + _n * 0x10000) /* UART Interrupt Enable Register */
#define S3C2510_UTXBUF(_n) REG_8 (0x0006000C + _n * 0x10000) /* UART Transmit Data Register */
#define S3C2510_URXBUF(_n) REG_8 (0x00060010 + _n * 0x10000) /* UART Receive Data Register */
#define S3C2510_UBRD(_n) REG_16(0x00060014 + _n * 0x10000) /* UART Baud Rate Divisor Register */
#define S3C2510_UCHAR1(_n) REG_32(0x00060018 + _n * 0x10000) /* UART Control Character 1 Register */
#define S3C2510_UCHAR2(_n) REG_32(0x0006001C + _n * 0x10000) /* UART Control Character 2 Register */
#define S3C2510_HUCHABB(_n) REG_32(0x00060100 + _n * 0x10000) /* High Speed UART Autobaud Boundary Register */
#define S3C2510_HUCHABT(_n) REG_32(0x00060104 + _n * 0x10000) /* High Speed UART Autobaud Table Register */
/* UART Control Register Bit Definitions */
#define S3C2510_HUCON_RTSRTR_MASK 0x80000000 /* RTS/RTR Selection */
#define S3C2510_HUCON_RTSRTR_RTS 0x00000000 /* RTS */
#define S3C2510_HUCON_RTSRTR_RTR 0x80000000 /* RTR */
#define S3C2510_UCON_ECHO 0x40000000 /* Echo Mode Enable */
#define S3C2510_UCON_SFEN 0x20000000 /* Software Flow Control Enable */
#define S3C2510_HUCON_HFEN 0x10000000 /* Hardware Flow Control Enable */
#define S3C2510_HUCON_RTS 0x02000000 /* Request To Send to Pin */
#define S3C2510_HUCON_DTR 0x01000000 /* Data Terminal Ready to Pin */
#define S3C2510_HUCON_RFTL_MASK 0x00C00000 /* Receive FIFO Trigger Level */
#define S3C2510_HUCON_RFTL_1 0x00000000 /* 30/32 Byte */
#define S3C2510_HUCON_RFTL_8 0x00400000 /* 24/32 Byte */
#define S3C2510_HUCON_RFTL_18 0x00800000 /* 16/32 Byte */
#define S3C2510_HUCON_RFTL_28 0x00C00000 /* 8/32 Byte */
#define S3C2510_HUCON_TFTL_MASK 0x00300000 /* Transmit FIFO Trigger Level */
#define S3C2510_HUCON_TFTL_30 0x00000000 /* 30/32 Byte */
#define S3C2510_HUCON_TFTL_24 0x00100000 /* 24/32 Byte */
#define S3C2510_HUCON_TFTL_16 0x00200000 /* 16/32 Byte */
#define S3C2510_HUCON_TFTL_8 0x00300000 /* 8/32 Byte */
#define S3C2510_HUCON_RFRST 0x00080000 /* Receive FIFO Reset */
#define S3C2510_HUCON_TFRST 0x00040000 /* Transmit FIFO Reset */
#define S3C2510_HUCON_RFEN 0x00020000 /* Receive FIFO Enable */
#define S3C2510_HUCON_TFEN 0x00010000 /* Transmit FIFO Enable */
#define S3C2510_UCON_IR 0x00004000 /* Infra-Red Mode */
#define S3C2510_UCON_WL_MASK 0x00003000 /* Word Length */
#define S3C2510_UCON_WL_5 0x00000000 /* 5 Bits */
#define S3C2510_UCON_WL_6 0x00001000 /* 6 Bits */
#define S3C2510_UCON_WL_7 0x00002000 /* 7 Bits */
#define S3C2510_UCON_WL_8 0x00003000 /* 8 Bits */
#define S3C2510_UCON_STB_MASK 0x00000800 /* Number of Stop Bits */
#define S3C2510_UCON_STB_1 0x00000000 /* One Stop Bit per Frame */
#define S3C2510_UCON_STB_2 0x00000800 /* Two Stop Bit per Frame */
#define S3C2510_UCON_PMD_MASK 0x00000700 /* Parity Mode */
#define S3C2510_UCON_PMD_NO 0x00000000 /* No Parity */
#define S3C2510_UCON_PMD_ODD 0x00000400 /* Odd Parity */
#define S3C2510_UCON_PMD_EVEN 0x00000500 /* Even Parity */
#define S3C2510_UCON_PMD_1 0x00000600 /* Parity is Forced/Checked as a '1' */
#define S3C2510_UCON_PMD_0 0x00000700 /* Parity is Forced/Checked as a '0' */
#define S3C2510_UCON_LOOPB 0x00000080 /* Loop-Back Enable */
#define S3C2510_HUCON_AUBD 0x00000040 /* Auto Baud Rate Detecte */
#define S3C2510_UCON_SCSEL_MASK 0x00000020 /* Serial Clock Select */
#define S3C2510_UCON_SCSEL_PCLK2 0x00000000 /* Internal (PCLK2 = PCLK / 2) */
#define S3C2510_UCON_SCSEL_UCLK 0x00000020 /* External */
#define S3C2510_UCON_SBR 0x00000010 /* Send Break */
#define S3C2510_UCON_RMODE_MASK 0x0000000C /* Receive Mode */
#define S3C2510_UCON_RMODE_DIS 0x00000000 /* Disable RX Mode */
#define S3C2510_UCON_RMODE_CPU 0x00000004 /* CPU Request */
#define S3C2510_UCON_RMODE_GDMA 0x00000008 /* GDMA Request */
#define S3C2510_UCON_RMODE_RESERVED 0x0000000C /* Reserved */
#define S3C2510_UCON_TMODE_MASK 0x00000003 /* Transmit Mode */
#define S3C2510_UCON_TMODE_DIS 0x00000000 /* Disable TX Mode */
#define S3C2510_UCON_TMODE_CPU 0x00000001 /* CPU Request */
#define S3C2510_UCON_TMODE_GDMA 0x00000002 /* GDMA Request */
#define S3C2510_UCON_TMODE_RESERVED 0x00000003 /* Reserved */
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