📄 s3c2510.h
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#define S3C2510_MUXBCON_TMA2_1CYCL 0x00000040 /* 1 Cycle */
#define S3C2510_MUXBCON_TMA2_2CYCL 0x00000080 /* 2 Cycle */
#define S3C2510_MUXBCON_TMA2_3CYCL 0x000000C0 /* 3 Cycle */
#define S3C2510_MUXBCON_TMA2_4CYCL 0x00000100 /* 4 Cycle */
#define S3C2510_MUXBCON_TMA2_5CYCL 0x00000140 /* 5 Cycle */
#define S3C2510_MUXBCON_TMA2_6CYCL 0x00000180 /* 6 Cycle */
#define S3C2510_MUXBCON_TMA2_7CYCL 0x000001C0 /* 7 Cycle */
#define S3C2510_MUXBCON_TMA2_8CYCL 0x00000000 /* 8 Cycle */
#define S3C2510_MUXBCON_TMA1_MASK 0x00000038 /* Muxed Bus Address Cycle for Bank 1 */
#define S3C2510_MUXBCON_TMA1_1CYCL 0x00000008 /* 1 Cycle */
#define S3C2510_MUXBCON_TMA1_2CYCL 0x00000010 /* 2 Cycle */
#define S3C2510_MUXBCON_TMA1_3CYCL 0x00000018 /* 3 Cycle */
#define S3C2510_MUXBCON_TMA1_4CYCL 0x00000020 /* 4 Cycle */
#define S3C2510_MUXBCON_TMA1_5CYCL 0x00000028 /* 5 Cycle */
#define S3C2510_MUXBCON_TMA1_6CYCL 0x00000030 /* 6 Cycle */
#define S3C2510_MUXBCON_TMA1_7CYCL 0x00000038 /* 7 Cycle */
#define S3C2510_MUXBCON_TMA1_8CYCL 0x00000000 /* 8 Cycle */
#define S3C2510_MUXBCON_TMA0_MASK 0x00000007 /* Muxed Bus Address Cycle for Bank 0 */
#define S3C2510_MUXBCON_TMA0_1CYCL 0x00000001 /* 1 Cycle */
#define S3C2510_MUXBCON_TMA0_2CYCL 0x00000002 /* 2 Cycle */
#define S3C2510_MUXBCON_TMA0_3CYCL 0x00000003 /* 3 Cycle */
#define S3C2510_MUXBCON_TMA0_4CYCL 0x00000004 /* 4 Cycle */
#define S3C2510_MUXBCON_TMA0_5CYCL 0x00000005 /* 5 Cycle */
#define S3C2510_MUXBCON_TMA0_6CYCL 0x00000006 /* 6 Cycle */
#define S3C2510_MUXBCON_TMA0_7CYCL 0x00000007 /* 7 Cycle */
#define S3C2510_MUXBCON_TMA0_8CYCL 0x00000000 /* 8 Cycle */
/* Wait Control Register Bit Definitions */
#define S3C2510_WAITCON_COHDIS7 0x00800000 /* TCOH Disable for Bank 7 */
#define S3C2510_WAITCON_COHDIS6 0x00400000 /* TCOH Disable for Bank 6 */
#define S3C2510_WAITCON_COHDIS5 0x00200000 /* TCOH Disable for Bank 5 */
#define S3C2510_WAITCON_COHDIS4 0x00100000 /* TCOH Disable for Bank 4 */
#define S3C2510_WAITCON_COHDIS3 0x00080000 /* TCOH Disable for Bank 3 */
#define S3C2510_WAITCON_COHDIS2 0x00040000 /* TCOH Disable for Bank 2 */
#define S3C2510_WAITCON_COHDIS1 0x00020000 /* TCOH Disable for Bank 1 */
#define S3C2510_WAITCON_COHDIS0 0x00010000 /* TCOH Disable for Bank 0 */
#define S3C2510_WAITCON_EWAITEN7 0x00008000 /* External Wait Enable for Bank 7 */
#define S3C2510_WAITCON_EWAITEN6 0x00004000 /* External Wait Enable for Bank 6 */
#define S3C2510_WAITCON_EWAITEN5 0x00002000 /* External Wait Enable for Bank 5 */
#define S3C2510_WAITCON_EWAITEN4 0x00001000 /* External Wait Enable for Bank 4 */
#define S3C2510_WAITCON_EWAITEN3 0x00000800 /* External Wait Enable for Bank 3 */
#define S3C2510_WAITCON_EWAITEN2 0x00000400 /* External Wait Enable for Bank 2 */
#define S3C2510_WAITCON_EWAITEN1 0x00000200 /* External Wait Enable for Bank 1 */
#define S3C2510_WAITCON_EWAITEN0 0x00000100 /* External Wait Enable for Bank 0 */
#define S3C2510_WAITCON_NREADY7 0x00000080 /* nWait / nReady Select for Bank 7 */
#define S3C2510_WAITCON_NREADY6 0x00000040 /* nWait / nReady Select for Bank 6 */
#define S3C2510_WAITCON_NREADY5 0x00000020 /* nWait / nReady Select for Bank 5 */
#define S3C2510_WAITCON_NREADY4 0x00000010 /* nWait / nReady Select for Bank 4 */
#define S3C2510_WAITCON_NREADY3 0x00000008 /* nWait / nReady Select for Bank 3 */
#define S3C2510_WAITCON_NREADY2 0x00000004 /* nWait / nReady Select for Bank 2 */
#define S3C2510_WAITCON_NREADY1 0x00000002 /* nWait / nReady Select for Bank 1 */
#define S3C2510_WAITCON_NREADY0 0x00000001 /* nWait / nReady Select for Bank 0 */
/*******************************************************************************
S3C2510 SDRAM Controller Special Registers
*******************************************************************************/
#define S3C2510_SDRAMCFG0 REG_32(0x00020000) /* Configuration Register 0 */
#define S3C2510_SDRAMCFG1 REG_32(0x00020004) /* Configuration Register 1 */
#define S3C2510_SDRAMCFG2 REG_32(0x00020008) /* Configuration Register 2 */
#define S3C2510_SDRAMCFG3 REG_32(0x0002000C) /* Configuration Register 3 */
/* SDRAM Configuration Register 0 Bit Definitions */
#define S3C2510_SDRAMCFG0_RAS_MASK 0x000F0000 /* Row Active Time */
#define S3C2510_SDRAMCFG0_RAS_1CYCL 0x00000000 /* 1 Cycle */
#define S3C2510_SDRAMCFG0_RAS_2CYCL 0x00010000 /* 2 Cycle */
#define S3C2510_SDRAMCFG0_RAS_3CYCL 0x00020000 /* 3 Cycle */
#define S3C2510_SDRAMCFG0_RAS_4CYCL 0x00030000 /* 4 Cycle */
#define S3C2510_SDRAMCFG0_RAS_5CYCL 0x00040000 /* 5 Cycle */
#define S3C2510_SDRAMCFG0_RAS_6CYCL 0x00050000 /* 6 Cycle */
#define S3C2510_SDRAMCFG0_RAS_7CYCL 0x00060000 /* 7 Cycle */
#define S3C2510_SDRAMCFG0_RAS_8CYCL 0x00070000 /* 8 Cycle */
#define S3C2510_SDRAMCFG0_RAS_9CYCL 0x00080000 /* 9 Cycle */
#define S3C2510_SDRAMCFG0_RAS_10CYCL 0x00090000 /* 10 Cycle */
#define S3C2510_SDRAMCFG0_RAS_11CYCL 0x000A0000 /* 11 Cycle */
#define S3C2510_SDRAMCFG0_RAS_12CYCL 0x000B0000 /* 12 Cycle */
#define S3C2510_SDRAMCFG0_RAS_13CYCL 0x000C0000 /* 13 Cycle */
#define S3C2510_SDRAMCFG0_RAS_14CYCL 0x000D0000 /* 14 Cycle */
#define S3C2510_SDRAMCFG0_RAS_15CYCL 0x000E0000 /* 15 Cycle */
#define S3C2510_SDRAMCFG0_RAS_16CYCL 0x000F0000 /* 16 Cycle */
#define S3C2510_SDRAMCFG0_RC_MASK 0x0000F000 /* Row Cycle */
#define S3C2510_SDRAMCFG0_RC_1CYCL 0x00000000 /* 1 Cycle */
#define S3C2510_SDRAMCFG0_RC_2CYCL 0x00001000 /* 2 Cycle */
#define S3C2510_SDRAMCFG0_RC_3CYCL 0x00002000 /* 3 Cycle */
#define S3C2510_SDRAMCFG0_RC_4CYCL 0x00003000 /* 4 Cycle */
#define S3C2510_SDRAMCFG0_RC_5CYCL 0x00004000 /* 5 Cycle */
#define S3C2510_SDRAMCFG0_RC_6CYCL 0x00005000 /* 6 Cycle */
#define S3C2510_SDRAMCFG0_RC_7CYCL 0x00006000 /* 7 Cycle */
#define S3C2510_SDRAMCFG0_RC_8CYCL 0x00007000 /* 8 Cycle */
#define S3C2510_SDRAMCFG0_RC_9CYCL 0x00008000 /* 9 Cycle */
#define S3C2510_SDRAMCFG0_RC_10CYCL 0x00009000 /* 10 Cycle */
#define S3C2510_SDRAMCFG0_RC_11CYCL 0x0000A000 /* 11 Cycle */
#define S3C2510_SDRAMCFG0_RC_12CYCL 0x0000B000 /* 12 Cycle */
#define S3C2510_SDRAMCFG0_RC_13CYCL 0x0000C000 /* 13 Cycle */
#define S3C2510_SDRAMCFG0_RC_14CYCL 0x0000D000 /* 14 Cycle */
#define S3C2510_SDRAMCFG0_RC_15CYCL 0x0000E000 /* 15 Cycle */
#define S3C2510_SDRAMCFG0_RC_16CYCL 0x0000F000 /* 16 Cycle */
#define S3C2510_SDRAMCFG0_RCD_MASK 0x00000C00 /* RAS to CAS Delay */
#define S3C2510_SDRAMCFG0_RCD_1CYCL 0x00000000 /* 1 Cycle */
#define S3C2510_SDRAMCFG0_RCD_2CYCL 0x00000400 /* 2 Cycle */
#define S3C2510_SDRAMCFG0_RCD_3CYCL 0x00000800 /* 3 Cycle */
#define S3C2510_SDRAMCFG0_RCD_4CYCL 0x00000C00 /* 4 Cycle */
#define S3C2510_SDRAMCFG0_RP_MASK 0x00000300 /* Row Pre-charge Time */
#define S3C2510_SDRAMCFG0_RP_1CYCL 0x00000000 /* 1 Cycle */
#define S3C2510_SDRAMCFG0_RP_2CYCL 0x00000100 /* 2 Cycle */
#define S3C2510_SDRAMCFG0_RP_3CYCL 0x00000200 /* 3 Cycle */
#define S3C2510_SDRAMCFG0_RP_4CYCL 0x00000300 /* 4 Cycle */
#define S3C2510_SDRAMCFG0_D1_MASK 0x000000C0 /* SDRAM Device Density of Bank 1 */
#define S3C2510_SDRAMCFG0_D1_16M 0x00000000 /* 16M */
#define S3C2510_SDRAMCFG0_D1_64M 0x00000040 /* 64M */
#define S3C2510_SDRAMCFG0_D1_128M 0x00000080 /* 128M */
#define S3C2510_SDRAMCFG0_D1_256M 0x000000C0 /* 256M */
#define S3C2510_SDRAMCFG0_D0_MASK 0x00000030 /* SDRAM Device Density of Bank 0 */
#define S3C2510_SDRAMCFG0_D0_16M 0x00000000 /* 16M */
#define S3C2510_SDRAMCFG0_D0_64M 0x00000010 /* 64M */
#define S3C2510_SDRAMCFG0_D0_128M 0x00000020 /* 128M */
#define S3C2510_SDRAMCFG0_D0_256M 0x00000030 /* 256M */
#define S3C2510_SDRAMCFG0_CL_MASK 0x0000000C /* CAS Latency */
#define S3C2510_SDRAMCFG0_CL_1CYCL 0x00000004 /* 1 Cycle */
#define S3C2510_SDRAMCFG0_CL_2CYCL 0x00000008 /* 2 Cycle */
#define S3C2510_SDRAMCFG0_CL_3CYCL 0x0000000C /* 3 Cycle */
#define S3C2510_SDRAMCFG0_AP_MASK 0x00000002 /* Auto Pre-charge control for SDRAM access */
#define S3C2510_SDRAMCFG0_AP_AUTO 0x00000000 /* Auto Pre-charge */
#define S3C2510_SDRAMCFG0_AP_NOAUTO 0x00000002 /* No Auto Pre-charge */
#define S3C2510_SDRAMCFG0_XW_MASK 0x00000001 /* External Data Bus Width = 16 Bits */
#define S3C2510_SDRAMCFG0_XW_32 0x00000000 /* External Data Bus Width = 32 Bits */
#define S3C2510_SDRAMCFG0_XW_16 0x00000001 /* External Data Bus Width = 16 Bits */
/* SDRAM Configuration Register 1 Bit Definitions */
#define S3C2510_SDRAMCFG1_BUSY 0x00000008 /* Control Bits for SDRAM Device Init */
#define S3C2510_SDRAMCFG1_WBUF 0x00000004 /* Write Buffer Enable */
#define S3C2510_SDRAMCFG1_INIT_MASK 0x00000003 /* Row Active Time */
#define S3C2510_SDRAMCFG1_INIT_NORMAL 0x00000000 /* Normal Operation */
#define S3C2510_SDRAMCFG1_INIT_PALL 0x00000001 /* Auto Issue PALL */
#define S3C2510_SDRAMCFG1_INIT_MRS 0x00000002 /* Auto Issue MRS */
/* SDRAM Configuration Register 2 Bit Definitions */
#define S3C2510_SDRAMCFG2_REFRESH_MASK 0x0000FFFF /* SDRAM Refresh Cycle */
/* SDRAM Configuration Register 3 Bit Definitions */
#define S3C2510_SDRAMCFG3_WBTO_MASK 0x0000FFFF /* Write Buffer Timeout Delay Time */
/*******************************************************************************
S3C2510 I/O Port Special Registers
*******************************************************************************/
#define S3C2510_IOPMOD1 REG_32(0x00030000) /* I/O Port Mode Select Lower Register */
#define S3C2510_IOPMOD2 REG_32(0x00030004) /* I/O Port Mode Select Upper Register */
#define S3C2510_IOPFUNC1 REG_32(0x00030008) /* I/O Port Function Select Lower Register */
#define S3C2510_IOPFUNC2 REG_32(0x0003000C) /* I/O Port Function Select Upper Register */
#define S3C2510_IOPDMA REG_32(0x00030010) /* I/O Port Special Function for DMA */
#define S3C2510_IOPINT REG_32(0x00030014) /* I/O Port Special Function for External Interrupt */
#define S3C2510_IOPINTPEND REG_32(0x00030018) /* External Interrupt Clear Register */
#define S3C2510_IOPDATA1 REG_32(0x0003001C) /* I/O Port Data Register */
#define S3C2510_IOPDATA2 REG_32(0x00030020) /* I/O Port Data Register */
#define S3C2510_IOPDRV1 REG_32(0x00030024) /* I/O Port Drive Control Register */
#define S3C2510_IOPDRV2 REG_32(0x00030028) /* I/O Port Drive Control Register */
/*******************************************************************************
S3C2510 32-Bit Timer Special Registers
*******************************************************************************/
#define S3C2510_TMOD REG_32(0x00040000) /* Timer Mode Register */
#define S3C2510_TIC REG_32(0x00040004) /* Timer Interrupt Clear Register */
#define S3C2510_WDT REG_32(0x00040008) /* Watchdog Timer Register */
#define S3C2510_TDATA0 REG_32(0x00040010) /* Timer 0 Data Register */
#define S3C2510_TCNT0 REG_32(0x00040014) /* Timer 0 Count Register */
#define S3C2510_TDATA1 REG_32(0x00040018) /* Timer 1 Data Register */
#define S3C2510_TCNT1 REG_32(0x0004001C) /* Timer 1 Count Register */
#define S3C2510_TDATA2 REG_32(0x00040020) /* Timer 2 Data Register */
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