📄 s3c2510.h
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#define S3C2510_WAITCON REG_32(0x00010024) /* Wait Control Register */
/* Bank Control Register Bit Definitions */
#define S3C2510_BCON_DW_MASK 0xC0000000 /* Physical Memory Data Bus Width */
#define S3C2510_BCON_DW_8 0x40000000 /* 8 Bits */
#define S3C2510_BCON_DW_16 0x80000000 /* 16 Bits */
#define S3C2510_BCON_DW_32 0xC0000000 /* 32 Bits */
#define S3C2510_BCON_PMC_MASK 0x30000000 /* Page Mode Configuration */
#define S3C2510_BCON_PMC_NORMAL 0x00000000 /* Normal ROM or External I/O */
#define S3C2510_BCON_PMC_4 0x10000000 /* 4 Word Page */
#define S3C2510_BCON_PMC_8 0x20000000 /* 8 Word Page */
#define S3C2510_BCON_PMC_16 0x30000000 /* 16 Word Page */
#define S3C2510_BCON_BS_MASK 0x0F000000 /* Bank Size */
#define S3C2510_BCON_BS_DIS 0x00000000 /* Disable */
#define S3C2510_BCON_BS_1M 0x01000000 /* 1M */
#define S3C2510_BCON_BS_2M 0x02000000 /* 2M */
#define S3C2510_BCON_BS_4M 0x03000000 /* 4M */
#define S3C2510_BCON_BS_8M 0x04000000 /* 8M */
#define S3C2510_BCON_BS_16M 0x05000000 /* 16M */
#define S3C2510_BCON_IS_MASK 0x00800000 /* nWBE Interface Selection */
#define S3C2510_BCON_IS_8 0x00000000 /* 8 Bits */
#define S3C2510_BCON_IS_16 0x00800000 /* 16 Bits */
#define S3C2510_BCON_TACC_MASK 0x001F0000 /* Access Cycle (nOE low time) */
#define S3C2510_BCON_TACC_3CYCL 0x00030000 /* 3 Cycle */
#define S3C2510_BCON_TACC_4CYCL 0x00040000 /* 4 Cycle */
#define S3C2510_BCON_TACC_5CYCL 0x00050000 /* 5 Cycle */
#define S3C2510_BCON_TACC_6CYCL 0x00060000 /* 6 Cycle */
#define S3C2510_BCON_TACC_7CYCL 0x00070000 /* 7 Cycle */
#define S3C2510_BCON_TACC_8CYCL 0x00080000 /* 8 Cycle */
#define S3C2510_BCON_TACC_9CYCL 0x00090000 /* 9 Cycle */
#define S3C2510_BCON_TACC_10CYCL 0x000A0000 /* 10 Cycle */
#define S3C2510_BCON_TACC_11CYCL 0x000B0000 /* 11 Cycle */
#define S3C2510_BCON_TACC_12CYCL 0x000C0000 /* 12 Cycle */
#define S3C2510_BCON_TACC_13CYCL 0x000D0000 /* 13 Cycle */
#define S3C2510_BCON_TACC_14CYCL 0x000E0000 /* 14 Cycle */
#define S3C2510_BCON_TACC_15CYCL 0x000F0000 /* 15 Cycle */
#define S3C2510_BCON_TACC_16CYCL 0x00100000 /* 16 Cycle */
#define S3C2510_BCON_TACC_17CYCL 0x00110000 /* 17 Cycle */
#define S3C2510_BCON_TACC_18CYCL 0x00120000 /* 18 Cycle */
#define S3C2510_BCON_TACC_19CYCL 0x00130000 /* 19 Cycle */
#define S3C2510_BCON_TACC_20CYCL 0x00140000 /* 20 Cycle */
#define S3C2510_BCON_TACC_21CYCL 0x00150000 /* 21 Cycle */
#define S3C2510_BCON_TACC_22CYCL 0x00160000 /* 22 Cycle */
#define S3C2510_BCON_TACC_23CYCL 0x00170000 /* 23 Cycle */
#define S3C2510_BCON_TACC_24CYCL 0x00180000 /* 24 Cycle */
#define S3C2510_BCON_TACC_25CYCL 0x00190000 /* 25 Cycle */
#define S3C2510_BCON_TACC_26CYCL 0x001A0000 /* 26 Cycle */
#define S3C2510_BCON_TACC_27CYCL 0x001B0000 /* 27 Cycle */
#define S3C2510_BCON_TACC_28CYCL 0x001C0000 /* 28 Cycle */
#define S3C2510_BCON_TACC_29CYCL 0x001D0000 /* 29 Cycle */
#define S3C2510_BCON_TACC_30CYCL 0x001E0000 /* 30 Cycle */
#define S3C2510_BCON_TACC_31CYCL 0x001F0000 /* 31 Cycle */
#define S3C2510_BCON_TPA_MASK 0x0000F000 /* Page Address Access Cycle */
#define S3C2510_BCON_TPA_0CYCL 0x00000000 /* 0 Cycle */
#define S3C2510_BCON_TPA_1CYCL 0x00001000 /* 1 Cycle */
#define S3C2510_BCON_TPA_2CYCL 0x00002000 /* 2 Cycle */
#define S3C2510_BCON_TPA_3CYCL 0x00003000 /* 3 Cycle */
#define S3C2510_BCON_TPA_4CYCL 0x00004000 /* 4 Cycle */
#define S3C2510_BCON_TPA_5CYCL 0x00005000 /* 5 Cycle */
#define S3C2510_BCON_TPA_6CYCL 0x00006000 /* 6 Cycle */
#define S3C2510_BCON_TPA_7CYCL 0x00007000 /* 7 Cycle */
#define S3C2510_BCON_TPA_8CYCL 0x00008000 /* 8 Cycle */
#define S3C2510_BCON_TPA_9CYCL 0x00009000 /* 9 Cycle */
#define S3C2510_BCON_TPA_10CYCL 0x0000A000 /* 10 Cycle */
#define S3C2510_BCON_TPA_11CYCL 0x0000B000 /* 11 Cycle */
#define S3C2510_BCON_TPA_12CYCL 0x0000C000 /* 12 Cycle */
#define S3C2510_BCON_TPA_13CYCL 0x0000D000 /* 13 Cycle */
#define S3C2510_BCON_TPA_14CYCL 0x0000E000 /* 14 Cycle */
#define S3C2510_BCON_TPA_15CYCL 0x0000F000 /* 15 Cycle */
#define S3C2510_BCON_TACS_MASK 0x00000F00 /* Address Setup Time */
#define S3C2510_BCON_TACS_0CYCL 0x00000000 /* 0 Cycle */
#define S3C2510_BCON_TACS_1CYCL 0x00000100 /* 1 Cycle */
#define S3C2510_BCON_TACS_2CYCL 0x00000200 /* 2 Cycle */
#define S3C2510_BCON_TACS_3CYCL 0x00000300 /* 3 Cycle */
#define S3C2510_BCON_TACS_4CYCL 0x00000400 /* 4 Cycle */
#define S3C2510_BCON_TACS_5CYCL 0x00000500 /* 5 Cycle */
#define S3C2510_BCON_TACS_6CYCL 0x00000600 /* 6 Cycle */
#define S3C2510_BCON_TACS_7CYCL 0x00000700 /* 7 Cycle */
#define S3C2510_BCON_TACS_8CYCL 0x00000800 /* 8 Cycle */
#define S3C2510_BCON_TACS_9CYCL 0x00000900 /* 9 Cycle */
#define S3C2510_BCON_TACS_10CYCL 0x00000A00 /* 10 Cycle */
#define S3C2510_BCON_TACS_11CYCL 0x00000B00 /* 11 Cycle */
#define S3C2510_BCON_TACS_12CYCL 0x00000C00 /* 12 Cycle */
#define S3C2510_BCON_TACS_13CYCL 0x00000D00 /* 13 Cycle */
#define S3C2510_BCON_TACS_14CYCL 0x00000E00 /* 14 Cycle */
#define S3C2510_BCON_TACS_15CYCL 0x00000F00 /* 15 Cycle */
#define S3C2510_BCON_TCOS_MASK 0x000000F0 /* Chip Selection Setup Time (on nOE) */
#define S3C2510_BCON_TCOS_0CYCL 0x00000000 /* 0 Cycle */
#define S3C2510_BCON_TCOS_1CYCL 0x00000010 /* 1 Cycle */
#define S3C2510_BCON_TCOS_2CYCL 0x00000020 /* 2 Cycle */
#define S3C2510_BCON_TCOS_3CYCL 0x00000030 /* 3 Cycle */
#define S3C2510_BCON_TCOS_4CYCL 0x00000040 /* 4 Cycle */
#define S3C2510_BCON_TCOS_5CYCL 0x00000050 /* 5 Cycle */
#define S3C2510_BCON_TCOS_6CYCL 0x00000060 /* 6 Cycle */
#define S3C2510_BCON_TCOS_7CYCL 0x00000070 /* 7 Cycle */
#define S3C2510_BCON_TCOS_8CYCL 0x00000080 /* 8 Cycle */
#define S3C2510_BCON_TCOS_9CYCL 0x00000090 /* 9 Cycle */
#define S3C2510_BCON_TCOS_10CYCL 0x000000A0 /* 10 Cycle */
#define S3C2510_BCON_TCOS_11CYCL 0x000000B0 /* 11 Cycle */
#define S3C2510_BCON_TCOS_12CYCL 0x000000C0 /* 12 Cycle */
#define S3C2510_BCON_TCOS_13CYCL 0x000000D0 /* 13 Cycle */
#define S3C2510_BCON_TCOS_14CYCL 0x000000E0 /* 14 Cycle */
#define S3C2510_BCON_TCOS_15CYCL 0x000000F0 /* 15 Cycle */
#define S3C2510_BCON_TCOH_MASK 0x0000000F /* Chip Selection Hold Time (on nOE) */
#define S3C2510_BCON_TCOH_0CYCL 0x00000000 /* 0 Cycle */
#define S3C2510_BCON_TCOH_1CYCL 0x00000001 /* 1 Cycle */
#define S3C2510_BCON_TCOH_2CYCL 0x00000002 /* 2 Cycle */
#define S3C2510_BCON_TCOH_3CYCL 0x00000003 /* 3 Cycle */
#define S3C2510_BCON_TCOH_4CYCL 0x00000004 /* 4 Cycle */
#define S3C2510_BCON_TCOH_5CYCL 0x00000005 /* 5 Cycle */
#define S3C2510_BCON_TCOH_6CYCL 0x00000006 /* 6 Cycle */
#define S3C2510_BCON_TCOH_7CYCL 0x00000007 /* 7 Cycle */
#define S3C2510_BCON_TCOH_8CYCL 0x00000008 /* 8 Cycle */
#define S3C2510_BCON_TCOH_9CYCL 0x00000009 /* 9 Cycle */
#define S3C2510_BCON_TCOH_10CYCL 0x0000000A /* 10 Cycle */
#define S3C2510_BCON_TCOH_11CYCL 0x0000000B /* 11 Cycle */
#define S3C2510_BCON_TCOH_12CYCL 0x0000000C /* 12 Cycle */
#define S3C2510_BCON_TCOH_13CYCL 0x0000000D /* 13 Cycle */
#define S3C2510_BCON_TCOH_14CYCL 0x0000000E /* 14 Cycle */
#define S3C2510_BCON_TCOH_15CYCL 0x0000000F /* 15 Cycle */
/* Muxed Bus Control Register Bit Definitions */
#define S3C2510_MUXBCON_MBE7 0x80000000 /* Address / Data Muxed Bus Enable for Bank 7 */
#define S3C2510_MUXBCON_MBE6 0x40000000 /* Address / Data Muxed Bus Enable for Bank 6 */
#define S3C2510_MUXBCON_MBE5 0x20000000 /* Address / Data Muxed Bus Enable for Bank 5 */
#define S3C2510_MUXBCON_MBE4 0x10000000 /* Address / Data Muxed Bus Enable for Bank 4 */
#define S3C2510_MUXBCON_MBE3 0x08000000 /* Address / Data Muxed Bus Enable for Bank 3 */
#define S3C2510_MUXBCON_MBE2 0x04000000 /* Address / Data Muxed Bus Enable for Bank 2 */
#define S3C2510_MUXBCON_MBE1 0x02000000 /* Address / Data Muxed Bus Enable for Bank 1 */
#define S3C2510_MUXBCON_MBE0 0x01000000 /* Address / Data Muxed Bus Enable for Bank 0 */
#define S3C2510_MUXBCON_TMA7_MASK 0x00E00000 /* Muxed Bus Address Cycle for Bank 7 */
#define S3C2510_MUXBCON_TMA7_1CYCL 0x00200000 /* 1 Cycle */
#define S3C2510_MUXBCON_TMA7_2CYCL 0x00400000 /* 2 Cycle */
#define S3C2510_MUXBCON_TMA7_3CYCL 0x00600000 /* 3 Cycle */
#define S3C2510_MUXBCON_TMA7_4CYCL 0x00800000 /* 4 Cycle */
#define S3C2510_MUXBCON_TMA7_5CYCL 0x00A00000 /* 5 Cycle */
#define S3C2510_MUXBCON_TMA7_6CYCL 0x00C00000 /* 6 Cycle */
#define S3C2510_MUXBCON_TMA7_7CYCL 0x00E00000 /* 7 Cycle */
#define S3C2510_MUXBCON_TMA7_8CYCL 0x00000000 /* 8 Cycle */
#define S3C2510_MUXBCON_TMA6_MASK 0x001C0000 /* Muxed Bus Address Cycle for Bank 6 */
#define S3C2510_MUXBCON_TMA6_1CYCL 0x00040000 /* 1 Cycle */
#define S3C2510_MUXBCON_TMA6_2CYCL 0x00080000 /* 2 Cycle */
#define S3C2510_MUXBCON_TMA6_3CYCL 0x000C0000 /* 3 Cycle */
#define S3C2510_MUXBCON_TMA6_4CYCL 0x00100000 /* 4 Cycle */
#define S3C2510_MUXBCON_TMA6_5CYCL 0x00140000 /* 5 Cycle */
#define S3C2510_MUXBCON_TMA6_6CYCL 0x00180000 /* 6 Cycle */
#define S3C2510_MUXBCON_TMA6_7CYCL 0x001C0000 /* 7 Cycle */
#define S3C2510_MUXBCON_TMA6_8CYCL 0x00000000 /* 8 Cycle */
#define S3C2510_MUXBCON_TMA5_MASK 0x00038000 /* Muxed Bus Address Cycle for Bank 5 */
#define S3C2510_MUXBCON_TMA5_1CYCL 0x00008000 /* 1 Cycle */
#define S3C2510_MUXBCON_TMA5_2CYCL 0x00010000 /* 2 Cycle */
#define S3C2510_MUXBCON_TMA5_3CYCL 0x00018000 /* 3 Cycle */
#define S3C2510_MUXBCON_TMA5_4CYCL 0x00020000 /* 4 Cycle */
#define S3C2510_MUXBCON_TMA5_5CYCL 0x00028000 /* 5 Cycle */
#define S3C2510_MUXBCON_TMA5_6CYCL 0x00030000 /* 6 Cycle */
#define S3C2510_MUXBCON_TMA5_7CYCL 0x00038000 /* 7 Cycle */
#define S3C2510_MUXBCON_TMA5_8CYCL 0x00000000 /* 8 Cycle */
#define S3C2510_MUXBCON_TMA4_MASK 0x00007000 /* Muxed Bus Address Cycle for Bank 4 */
#define S3C2510_MUXBCON_TMA4_1CYCL 0x00001000 /* 1 Cycle */
#define S3C2510_MUXBCON_TMA4_2CYCL 0x00002000 /* 2 Cycle */
#define S3C2510_MUXBCON_TMA4_3CYCL 0x00003000 /* 3 Cycle */
#define S3C2510_MUXBCON_TMA4_4CYCL 0x00004000 /* 4 Cycle */
#define S3C2510_MUXBCON_TMA4_5CYCL 0x00005000 /* 5 Cycle */
#define S3C2510_MUXBCON_TMA4_6CYCL 0x00006000 /* 6 Cycle */
#define S3C2510_MUXBCON_TMA4_7CYCL 0x00007000 /* 7 Cycle */
#define S3C2510_MUXBCON_TMA4_8CYCL 0x00000000 /* 8 Cycle */
#define S3C2510_MUXBCON_TMA3_MASK 0x00000E00 /* Muxed Bus Address Cycle for Bank 3 */
#define S3C2510_MUXBCON_TMA3_1CYCL 0x00000200 /* 1 Cycle */
#define S3C2510_MUXBCON_TMA3_2CYCL 0x00000400 /* 2 Cycle */
#define S3C2510_MUXBCON_TMA3_3CYCL 0x00000600 /* 3 Cycle */
#define S3C2510_MUXBCON_TMA3_4CYCL 0x00000800 /* 4 Cycle */
#define S3C2510_MUXBCON_TMA3_5CYCL 0x00000A00 /* 5 Cycle */
#define S3C2510_MUXBCON_TMA3_6CYCL 0x00000C00 /* 6 Cycle */
#define S3C2510_MUXBCON_TMA3_7CYCL 0x00000E00 /* 7 Cycle */
#define S3C2510_MUXBCON_TMA3_8CYCL 0x00000000 /* 8 Cycle */
#define S3C2510_MUXBCON_TMA2_MASK 0x000001C0 /* Muxed Bus Address Cycle for Bank 2 */
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