📄 s3c2510eth.h
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/* s3c2510Eth.h - SAMSUNG S3C2510 Ethernet network interface header */
/* Copyright 2002 SAMSUNG ELECTRONICS */
/*
modification history
--------------------
01a,08feb02,jmLee created.
*/
#ifndef __INCs3c2510Ethh
#define __INCs3c2510Ethh
#include "end.h"
#include "etherLib.h"
#include "miiLib.h"
#ifdef __cplusplus
extern "C" {
#endif
/* Ethernet Options */
#define ETH_FULL_DUPLEX /* Support Full-Duplex */
#define ETH_AUTO_NEGOTIATION /* Enable Auto-Negotiation */
#define ETH_10BT /* Support 10BaseT */
/* Ethernet Definitions */
#define ETH_DEV_NAME "secEnd" /* device name */
#define ETH_DEV_NAME_LEN 7 /* device name length (include terminating null) */
#define ETH_DEV_DESCRIPTION "SAMSUNG Ethernet Enhanced Network Driver"
#define SIZE_ETH_ADDR 6 /* Ethernet Address Length */
#define SIZE_ETH_HDR 14 /* Ethernet Header Length */
#if ((SIZE_ETH_HDR % 4) == 0)
#define SIZE_ETH_FB_HDR 8 /* Free Buffer Header */
#define SIZE_ETH_WA 0 /* Widget Align */
#elif ((SIZE_ETH_HDR % 4) == 1)
#define SIZE_ETH_FB_HDR 8 /* Free Buffer Header */
#define SIZE_ETH_WA 3 /* Widget Align */
#elif ((SIZE_ETH_HDR % 4) == 2)
#define SIZE_ETH_FB_HDR 8 /* Free Buffer Header */
#define SIZE_ETH_WA 2 /* Widget Align */
#else /* ((SIZE_ETH_HDR % 4) == 3) */
#define SIZE_ETH_FB_HDR 8 /* Free Buffer Header */
#define SIZE_ETH_WA 1 /* Widget Align */
#endif /* ((SIZE_ETH_HDR % 4) == 0) */
#define SIZE_ETH_CRC 0 /* CRC Length */
#define SIZE_ETH_MFLR (1500 + SIZE_ETH_HDR) /* Max Ethernet Frame Length of Receive, exclude CRC */
#define SIZE_ETH_MINFLR ( 46 + SIZE_ETH_HDR) /* Min Ethernet Frame Length of Receive, exclude CRC */
#define SIZE_ETH_MDMA 1520 /* Max DMA Length */
#if 0
/* Standard MII Register */
#define MII_CTRL_REG 0 /* Control Register */
#define MII_CTRL_RESET 0x8000 /* Reset, 0 = normal, 1 = PHY reset */
#define MII_CTRL_LOOPBACK_EN 0x4000 /* Loopback, 0 = normal, 1 = loopback */
#define MII_CTRL_100 0x2000 /* Speed Selection, 0 = 10mb, 1 = 100mb */
#define MII_CTRL_AN_EN 0x1000 /* Auto-Negotiation Enable */
#define MII_CTRL_POWER_DOWN_EN 0x0800 /* Power Down */
#define MII_CTRL_ISOLATE 0x0400 /* Isolate PHY from MII */
#define MII_CTRL_AN_RESTART 0x0200 /* Restart Auto Negotiation */
#define MII_CTRL_FDX_EN 0x0100 /* Enable full-duplex */
#define MII_CTRL_COL_TEST_EN 0x0080 /* Collision Test */
#define MII_STAT_REG 1 /* Status Register */
#define MII_STAT_100T4 0x8000 /* 100T4 capable */
#define MII_STAT_100X_FDX 0x4000 /* 100TX-FX FD capable */
#define MII_STAT_100X_HDX 0x2000 /* 100TX-FX HD capable */
#define MII_STAT_10T_FDX 0x1000 /* 10T FD capable */
#define MII_STAT_10T_HDX 0x0800 /* 10T HD capable */
#define MII_STAT_100T2_FDX 0x0400 /* 100T2 FD capable */
#define MII_STAT_100T2_HDX 0x0200 /* 100T2 HD capable */
#define MII_STAT_RSVD 0x0100 /* Reserved */
#define MII_STAT_MASTER_SLAVE_FAULT 0x0080 /* Master-Slave Configuration Fault */
#define MII_STAT_MF_PREAMBLE_SUP 0x0040 /* MF Preamble Supression */
#define MII_STAT_AN_COMPLETE 0x0020 /* Auto Negotiation Complete */
#define MII_STAT_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
#define MII_STAT_AN 0x0008 /* Auto-Neotiation Capable */
#define MII_STAT_LINK 0x0004 /* Link Status, 1 = up, 0 = down */
#define MII_STAT_JABBER 0x0002 /* Jabber Detect */
#define MII_STAT_EXT_CAP 0x0001 /* Extended Capability */
#define MII_PHY_ID1_REG 2 /* PHY Identification Register 1 */
#define MII_PHY_ID2_REG 3 /* PHY Identification Register 1 */
#define MII_AN_ADS_REG 4 /* Auto Negotiation Advertisement Register */
#define MII_AN_ADS_NEXT_PAGE 0x8000 /* Next Page */
#define MII_AN_ADS_RSVD1 0x4000 /* Reserved */
#define MII_AN_ADS_REMOTE_FAULT 0x2000 /* Remote Fault */
#define MII_AN_ADS_RSVD2 0x1800 /* Reserved */
#define MII_AN_ADS_PAUSE 0x0400 /* Pause operation is enabled for full-duplex links */
#define MII_AN_ADS_100T4 0x0200 /* 100T4 capable */
#define MII_AN_ADS_100X_FDX 0x0100 /* 100TX-FX full-duplex capable */
#define MII_AN_ADS_100X_HDX 0x0080 /* 100TX-FX half-duplex capable */
#define MII_AN_ADS_10T_FDX 0x0040 /* 10T full-duplex capable */
#define MII_AN_ADS_10T_HDX 0x0020 /* 10T half-duplex capable */
#define MII_AN_ADS_SEL_MASK 0x001F /* Selector Field */
#define MII_AN_ADS_SEL_802_3 0x0001 /* 802.3 */
#define MII_AN_ADS_SEL_802_9 0x0002 /* 802.9 */
#define MII_AN_PRTN_REG 5 /* Auto Negotiation Link Partner Ability Register */
#define MII_AN_PRTN_NEXT_PAGE 0x8000 /* Multiple Page capable */
#define MII_AN_PRTN_ACK 0x4000 /* Ack from Link Partner */
#define MII_AN_PRTN_REMOTE_FAULT 0x2000 /* Remote Fault */
#define MII_AN_PRTN_RSVD1 0x1800 /* Reserved */
#define MII_AN_PRTN_PAUSE 0x0400 /* Pause operation is enabled for full-duplex links */
#define MII_AN_PRTN_100T4 0x0200 /* 100T4 capable */
#define MII_AN_PRTN_100X_FDX 0x0100 /* 100TX-FX full-duplex capable */
#define MII_AN_PRTN_100X_HDX 0x0080 /* 100TX-FX half-duplex capable */
#define MII_AN_PRTN_10T_FDX 0x0040 /* 10T full-duplex capable */
#define MII_AN_PRTN_10T_HDX 0x0020 /* 10T half-duplex capable */
#define MII_AN_PRTN_SEL_MASK 0x001F /* Selector Field */
#define MII_AN_PRTN_SEL_802_3 0x0001 /* 802.3 */
#define MII_AN_PRTN_SEL_802_9 0x0002 /* 802.9 */
#define MII_AN_EXP_REG 6 /* Auto Negotiation Expansion */
#define MII_AN_NEXT_REG 7 /* Auto Negotiation Next Page Register */
#endif
/* LSI L80225 Specific MII Register */
#define L80225_STAT_REG 18 /* Status Output Register */
#define L80225_STAT_100 0x0080 /* 1:100M, 0:10M */
#define L80225_STAT_FDX 0x0040 /* 1:Full Duplex, 0:Half Duplex */
/* S3C2510 Ethernet Buffer Descriptor */
typedef struct s3c2510_eth_bd {
UINT32 pBuf;
#if _BYTE_ORDER==_BIG_ENDIAN
UINT16 status;
UINT16 length;
#else /* #if _BYTE_ORDER==_BIG_ENDIAN */
UINT16 length;
UINT16 status;
#endif /* #if _BYTE_ORDER==_BIG_ENDIAN */
} S3C2510_ETH_BD, *PETHRBD, *PETHTBD;
/* S3C2510 Ethernet Receive Buffer Descriptor Definitions */
#define S3C2510_ETH_RBD_O 0x8000 /* Ownership, 0:CPU, 1:BDMA */
#define S3C2510_ETH_RBD_B 0x4000 /* Skip BD */
#define S3C2510_ETH_RBD_S 0x2000 /* Start of Frame */
#define S3C2510_ETH_RBD_E 0x1000 /* End of Frame */
#define S3C2510_ETH_RBD_D 0x0800 /* BDMA Rx Done, First of Multiple */
#define S3C2510_ETH_RBD_BMSO 0x0400 /* BDMA Rx Maximum Size Over */
#define S3C2510_ETH_RBD_MHALTED 0x0200 /* MAC Rx Halted */
#define S3C2510_ETH_RBD_M10STAT 0x0100 /* MAC Rx 10M Status */
#define S3C2510_ETH_RBD_BDONE 0x0080 /* BDMA Rx Done */
#define S3C2510_ETH_RBD_MPARERR 0x0040 /* MAC Rx Parity Error */
#define S3C2510_ETH_RBD_MLONGERR 0x0020 /* MAC Rx Long Error */
#define S3C2510_ETH_RBD_MOVERFLOW 0x0010 /* MAC Rx Overflow */
#define S3C2510_ETH_RBD_MCRCERR 0x0008 /* MAC Rx CRC Error */
#define S3C2510_ETH_RBD_MALIGNERR 0x0004 /* MAC Rx Alignment Error */
/* S3C2510 Ethernet Transmit Buffer Descriptor Definitions */
#define S3C2510_ETH_TBD_O 0x8000 /* Ownership, 0:CPU, 1:BDMA */
#define S3C2510_ETH_TBD_MPAUSED 0x2000 /* MAC Tx Paused */
#define S3C2510_ETH_TBD_MHALTED 0x1000 /* MAC Tx Halted */
#define S3C2510_ETH_TBD_MSQEERR 0x0800 /* MAC Tx Signal Quality Error */
#define S3C2510_ETH_TBD_MDEFER 0x0400 /* MAC Tx Deferred Error */
#define S3C2510_ETH_TBD_MCOLL 0x0200 /* MAC Tx Collision is Occured */
#define S3C2510_ETH_TBD_MCOMP 0x0100 /* MAC Tx Completed */
#define S3C2510_ETH_TBD_MPARERR 0x0080 /* MAC Tx Parity Error */
#define S3C2510_ETH_TBD_MLATECOLL 0x0040 /* MAC Tx Late Collision */
#define S3C2510_ETH_TBD_MNOCARR 0x0020 /* MAC Tx No Carrier */
#define S3C2510_ETH_TBD_MDEFERERR 0x0010 /* MAC Tx Deferred Error */
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