rominit.s

S3c2510下的VXWORKS的BSP源代码（包括了以太网、串口、USB等等驱动）

        STR     r1, [r2]
#endif  /* UCLK_EXTERNAL */

#ifndef PCLK_EXTERNAL
        LDR     r2, =S3C2510_PPLLCON
        LDR     r1, =0x00010300 | (PPLL_FREQ - 8)           /* defined in config.h */
        STR     r1, [r2]
#endif  /* PCLK_EXTERNAL */
       
        /* Enable PLL Register and Remap. */
        LDR     r2, =S3C2510_SYSCFG
        LDR     r1, =S3C2510_SYSCFG_REMAP | \
                     S3C2510_SYSCFG_ARBF 
                     
                     /*
                     S3C2510_SYSCFG_UPLLREN | \
                     S3C2510_SYSCFG_CPLLREN | \
                     S3C2510_SYSCFG_SPLLREN                      
      				 */
        
#ifndef UCLK_EXTERNAL
        ORR     r1, r1, #S3C2510_SYSCFG_UPLLREN 
#endif  /* UCLK_EXTERNAL */
#ifndef PCLK_EXTERNAL
        ORR     r1, r1, #S3C2510_SYSCFG_PPLLREN
#endif  /* PCLK_EXTERNAL */
        STR     r1, [r2]
        
        
        /* Jump to the normal (higher) ROM position. */
        BX      r12

HiPosition:
        /* 
         * Now we are now executing in the normal (higher, still in ROM) position.
         * SDRAM is mapped to 0x00000000, and ROM is mapped to 0x80000000.
         */

        /* Initialize Bank Control Register. */

        /* Bank 0 - ROM (Boot Flash) */
        LDR     r2, =S3C2510_B0CON
        LDR     r1, =S3C2510_BCON_DW_16 | \
                     S3C2510_BCON_PMC_NORMAL | \
                     S3C2510_BCON_BS_1M | \
                     S3C2510_BCON_IS_8 | \
                     S3C2510_BCON_TACC_20CYCL | \
                     S3C2510_BCON_TPA_14CYCL | \
                     S3C2510_BCON_TACS_4CYCL | \
                     S3C2510_BCON_TCOS_8CYCL | \
                     S3C2510_BCON_TCOH_8CYCL
        STR     r1, [r2]

#ifdef  INCLUDE_FLASH
        /* Bank 1 - Flash (Application Flash) */
        LDR     r2, =S3C2510_B1CON
        LDR     r1, =S3C2510_BCON_DW_16 | \
                     S3C2510_BCON_PMC_NORMAL | \
                     S3C2510_BCON_BS_2M | \
                     S3C2510_BCON_IS_16 | \
                     S3C2510_BCON_TACC_20CYCL | \
                     S3C2510_BCON_TPA_14CYCL | \
                     S3C2510_BCON_TACS_4CYCL | \
                     S3C2510_BCON_TCOS_8CYCL | \
                     S3C2510_BCON_TCOH_8CYCL
        STR     r1, [r2]
#endif  /* INCLUDE_FLASH */

#ifdef  INCLUDE_LCD
        /* Bank 2 - LCD */
        LDR     r2, =S3C2510_B2CON
        LDR     r1, =S3C2510_BCON_DW_8 | \
                     S3C2510_BCON_PMC_NORMAL | \
                     S3C2510_BCON_BS_1M | \
                     S3C2510_BCON_IS_8 | \
                     S3C2510_BCON_TACC_20CYCL | \
                     S3C2510_BCON_TPA_14CYCL | \
                     S3C2510_BCON_TACS_4CYCL | \
                     S3C2510_BCON_TCOS_8CYCL | \
                     S3C2510_BCON_TCOH_8CYCL
        STR     r1, [r2]
#endif  /* INCLUDE_LCD */

#ifdef  INCLUDE_SRAM
        /* Bank 4 - SRAM */
        LDR     r2, =S3C2510_B4CON
        LDR     r1, =S3C2510_BCON_DW_32 | \
                     S3C2510_BCON_PMC_NORMAL | \
                     S3C2510_BCON_BS_1M | \
                     S3C2510_BCON_IS_16 | \
                     S3C2510_BCON_TACC_10CYCL | \
                     S3C2510_BCON_TPA_14CYCL | \
                     S3C2510_BCON_TACS_0CYCL | \
                     S3C2510_BCON_TCOS_0CYCL | \
                     S3C2510_BCON_TCOH_1CYCL
        STR     r1, [r2]
#endif  /* INCLUDE_SRAM */

        /* Initialize Muxed Bus Control Register. */
        LDR     r2, =S3C2510_MUXBCON
        LDR     r1, =S3C2510_MUXBCON_TMA7_3CYCL | \
                     S3C2510_MUXBCON_TMA6_3CYCL | \
                     S3C2510_MUXBCON_TMA5_3CYCL | \
                     S3C2510_MUXBCON_TMA4_3CYCL | \
                     S3C2510_MUXBCON_TMA3_3CYCL | \
                     S3C2510_MUXBCON_TMA2_3CYCL | \
                     S3C2510_MUXBCON_TMA1_3CYCL | \
                     S3C2510_MUXBCON_TMA0_3CYCL
        STR     r1, [r2]

        /* Initialize Wait Control Register. */
        LDR     r2, =S3C2510_WAITCON
        LDR     r1, =S3C2510_WAITCON_COHDIS7 | \
                     S3C2510_WAITCON_COHDIS6 | \
                     S3C2510_WAITCON_COHDIS5 | \
                     S3C2510_WAITCON_COHDIS4 | \
                     S3C2510_WAITCON_COHDIS3 | \
                     S3C2510_WAITCON_COHDIS2 | \
                     S3C2510_WAITCON_COHDIS1
        STR     r1, [r2]

        /* Initialize SDRAM configuration. */

        /* Wait 200us to allow SDRAM power and clocks to stabilize. */
        LDR     r1, =CPLL_FREQ*300                          /* defined in config.h */
sdram1:
        SUBS    r1, r1, #1
        BNE     sdram1

        /* PALL command to the SDRAM. */
        LDR     r2, =S3C2510_SDRAMCFG1
        MOV     r1, #S3C2510_SDRAMCFG1_INIT_PALL
        STR     r1, [r2]

        /* Initialize Refresh Timer Register. */
        LDR     r2, =S3C2510_SDRAMCFG2
        MOV     r1, #15
        STR     r1, [r2]

        /* Wait for a time period equivalent to 8 refresh cycles. */
        MOV     r1, #15*8
sdram2:
        SUBS    r1, r1, #1
        BNE     sdram2

        /* Initialize Refresh Timer Register. */
        LDR     r2, =S3C2510_SDRAMCFG2
        LDR     r1, =SDRAM_REFRESH_CYCL                     /* defined in config.h */
        STR     r1, [r2]

	/* Initialize SDRAM Configuration Register 0. */
        LDR     r2, =S3C2510_SDRAMCFG0
        LDR     r1, =S3C2510_SDRAMCFG0_RAS_6CYCL | \
                     S3C2510_SDRAMCFG0_RC_6CYCL | \
                     S3C2510_SDRAMCFG0_RCD_2CYCL | \
                     S3C2510_SDRAMCFG0_RP_4CYCL | \
                     S3C2510_SDRAMCFG0_D1_128M | \
                     S3C2510_SDRAMCFG0_D0_128M | \
                     S3C2510_SDRAMCFG0_CL_3CYCL | \
                     S3C2510_SDRAMCFG0_AP_NOAUTO | \
                     S3C2510_SDRAMCFG0_XW_32
        STR     r1, [r2]

        /* MRS command to the SDRAM. */
        LDR     r2, =S3C2510_SDRAMCFG1
        MOV     r1, #S3C2510_SDRAMCFG1_INIT_MRS
        STR     r1, [r2]

        /* Controller enters the normal mode. */
        LDR     r2, =S3C2510_SDRAMCFG1
        MOV     r1, #S3C2510_SDRAMCFG1_INIT_NORMAL
        STR     r1, [r2]

        /* Initialize SDRAM Configuration Register 1. */
        LDR     r2, =S3C2510_SDRAMCFG1
        MOV     r1, #0
        STR     r1, [r2]

        /* Initialize SDRAM Configuration Register 3. */
        LDR     r2, =S3C2510_SDRAMCFG3
        MOV     r1, #0
        STR     r1, [r2]

        /* Enable write buffer. */
        LDR     r2, =S3C2510_SDRAMCFG1
        MOV     r1, #S3C2510_SDRAMCFG1_WBUF  
        STR     r1, [r2] 

        /* Set write buffer timeout. */
        LDR     r2, =S3C2510_SDRAMCFG3
        LDR     r1, =SDRAM_REFRESH_CYCL                     /* defined in config.h */
        STR     r1, [r2]

        /*
         * End of DRAM initialisation.
         *
         * Initialize the stack pointer to just before where the
         * uncompress code, copied from ROM to RAM, will run.
         */
        LDR     sp, L$_STACK_ADDR
        MOV     fp, #0                                      /* zero frame pointer */

        /* Jump to C entry point in ROM: routine - entry point + ROM base */
        LDR     pc, L$_rStrtInRom

/******************************************************************************/

/*
 * PC-relative-addressable pointers - LDR Rn,=sym is broken
 * note "_" after "$" to stop preprocessor performing substitution
 */

        .balign 4

L$_HiPosition:
        .long   ROM_TEXT_ADRS + HiPosition - _romInit

L$_rStrtInRom:
        .long   ROM_TEXT_ADRS + _romStart - _romInit

L$_STACK_ADDR:
        .long   STACK_ADRS

L$_sysCacheUncachedAdrs:
        .long   SYS_CACHE_UNCACHED_ADRS