rominit.s

S3c2510下的VXWORKS的BSP源代码（包括了以太网、串口、USB等等驱动）

/* romInit.s - SAMSUNG S3C2510 ROM initialization module */

/* Copyright 2002 SAMSUNG ELECTRONICS */

/*
modification history
--------------------
01a,08feb02,jmLee   created.
*/

/*
DESCRIPTION
This module contains the entry code for VxWorks images that start running from
ROM, such as 'bootrom' and 'vxWorks_rom'. The entry point, romInit(), is the
first code executed on power-up. It performs the minimal setup needed to call
the generic C routine romStart() with parameter BOOT_COLD.

romInit() masks interrupts in the processor and the interrupt controller and
sets the initial stack pointer (to STACK_ADRS which is defined in configAll.h).
Other hardware and device initialization is performed later in the sysHwInit
routine in sysLib.c.

The routine sysToMonitor() jumps to a location after the beginning of romInit,
to perform a "warm boot". This entry point allows a parameter to be passed to
romStart().

The routines in this module don't use the "C" frame pointer %r11@ ! or establish
a stack frame.

SEE ALSO:
.I "ARM Architecture Reference Manual,"
.I "ARM 940T Technical Reference Manual",
.I "ARM Reference Peripherals Specification,"
.I "SAMSUNG S3C2510 Microcontroller User's Manual",
*/


#define _ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "config.h"
#include "regs.h"
#include "sysLib.h"
#include "arch/arm/mmuArmLib.h"
#include "drv/multi/s3c2510.h"

        /* internals */

        .globl  _romInit                                    /* start of system code */
        .globl  _sdata                                      /* start of data */

        /* externals */

        .extern _romStart                                   /* system initialization routine */

        .data
_sdata:
        .ascii  "12:34:56:78:"
	.balign	4

        .text
        .balign 4


/*******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
*/

_ARM_FUNCTION(_romInit)

        MOV     r0, #BOOT_COLD                              /* fall through to warm boot entry */
warm:
        B       start

        /* copyright notice appears at beginning of ROM (in TEXT segment) */

        .ascii  "Copyright 2002 SAMSUNG ELECTRONICS"
        .balign 4

start:
        /* 
         * There have been reports of problems with certain boards and certain
         * power supplies not coming up after a power-on reset, and adding a
         * delay(about 200 usec) at the start of romInit appears to help with this.
         */

        LDR     r1, =CPLL_FREQ*200                          /* load Count, defined in config.h */
delay:
        SUBS    r1, r1, #1
        BNE     delay

        /*
         * Set processor and MMU to known state as follows (we may have not
         * been entered from a reset). We must do this before setting the CPU
         * mode.
         *
         * MMU Control Register layout.
         *
         * bit
         *  0 P 0 Protection Unit Enable
         *  1 Z 0 Reserved (Should Be Zero)
         *  2 D 0 Data Cache Enable
         *  3 O 1 Reserved (Should Be One)
         *  4 O 1 Reserved (Should Be One)
         *  5 O 1 Reserved (Should Be One)
         *  6 O 1 Reserved (Should Be One)
         *  7 E 0 Endianness (0:Little, 1:Big)
         *  8 Z 0 Reserved (Should Be Zero)
         *  9 Z 0 Reserved (Should Be Zero)
         * 10 Z 0 Reserved (Should Be Zero)
         * 11 Z 0 Reserved (Should Be Zero)
         * 12 I 0 Instruction Cache Enable
         * 13 V 0 Alternate Vectors Select
         * 14 Z 0 Reserved (Should Be Zero)
         * .
         * .
         * 29 Z 0 Reserved (Should Be Zero)
         * 30 F 0 Fastbus Clocking Select
         * 31 A 0 Asynchoronous Clocking Select
         */

		/* Control LED display. */
		LDR	r1, =S3C2510_IOPMOD1
		LDR	r2, =0x0
		STR	r2, [r1]
		LDR	r1, =S3C2510_IOPDATA1
		LDR	r2, =0x33
		STR	r2, [r1]


        /* Initialize MMU Control Register. */
        LDR     r1, =MMU_INIT_VALUE                         /* defined in mmuArmLib.h */
        ORR     r1, r1, #CLOCK_MODE                         /* defined in config.h */
        MCR     CP_MMU, 0, r1, c1, c0, 0                    /* write to MMU CR */

        /* Drain write-buffer. */
        LDR     r1, L$_sysCacheUncachedAdrs                 /* R1 -> uncached area */
        LDR     r1, [r1]                                    /* drain write-buffer */

        /* Flush (invalidate) both caches. */
        MOV     r1, #0                                      /* data SBZ */
        MCR     CP_MMU, 0, r1, c7, c5, 0                    /* Flush (invalidate) all I-cache */
        MCR     CP_MMU, 0, r1, c7, c6, 0                    /* Flush (invalidate) all D-cache */

        /* Disable interrupts in CPU and switch to SVC32 mode. */
        MRS     r1, cpsr
        BIC     r1, r1, #MASK_MODE                          /* defined in arm.h */
        ORR     r1, r1, #MODE_SVC32 | I_BIT | F_BIT
        MSR     cpsr, r1

        /* Disable individual interrupts in the interrupt controller. */
        LDR     r2, =S3C2510_INTINTMASK
        LDR     r1, =S3C2510_INT_MASK_INTERNAL
        STR     r1, [r2]                                    /* disable all internal interrupt */
        LDR     r2, =S3C2510_EXTINTMASK
        LDR     r1, =S3C2510_INT_MASK_EXTERNAL
        STR     r1, [r2]                                    /* disable all external interrupt */

        /* Disable peripherals. */
        LDR     r2, =S3C2510_PCLKDIS
        LDR     r1, =S3C2510_PCLKDIS_SAR | \
                     S3C2510_PCLKDIS_PCI_PCCARD  | \
                     S3C2510_PCLKDIS_USBH | \
                     S3C2510_PCLKDIS_DES | \
                     S3C2510_PCLKDIS_I2C | \
                     S3C2510_PCLKDIS_IOP | \
                     S3C2510_PCLKDIS_WDT | \
                     S3C2510_PCLKDIS_TIMER5 | \
                     S3C2510_PCLKDIS_TIMER4 | \
                     S3C2510_PCLKDIS_TIMER3 | \
                     S3C2510_PCLKDIS_TIMER2 | \
                     S3C2510_PCLKDIS_TIMER1 | \
                     S3C2510_PCLKDIS_TIMER0 | \
                     S3C2510_PCLKDIS_HUART1 | \
                     S3C2510_PCLKDIS_HUART0 | \
                     S3C2510_PCLKDIS_CUART | \
                     S3C2510_PCLKDIS_USB | \
                     S3C2510_PCLKDIS_ETH1 | \
                     S3C2510_PCLKDIS_ETH0 | \
                     S3C2510_PCLKDIS_GDMA5 | \
                     S3C2510_PCLKDIS_GDMA4 | \
                     S3C2510_PCLKDIS_GDMA3 | \
                     S3C2510_PCLKDIS_GDMA2 | \
                     S3C2510_PCLKDIS_GDMA1 | \
                     S3C2510_PCLKDIS_GDMA0
        STR     r1, [r2]
		
		
		
        /* Load normal (higher) ROM position. */
        LDR     r12, L$_HiPosition

              
     
   
        /*
        * Initialize PLL Control Register.
        *
        * Output Clock = Input Clock * (M + 8) / ((P + 2) * (2 ^ S))
        */

/*
        LDR     r2, =S3C2510_CPLLCON
        LDR     r1, =0x00010300 | (CPLL_FREQ - 8)
        STR     r1, [r2]
    
    // Delay for clock stabilization //
	    LDR     r1, =CPLL_FREQ*100                          
delay1:
        SUBS    r1, r1, #1
        BNE     delay1

        LDR     r2, =S3C2510_SPLLCON
        LDR     r1, =0x00010300 | (SPLL_FREQ - 8)            
        STR     r1, [r2]
*/

#ifndef UCLK_EXTERNAL
        LDR     r2, =S3C2510_UPLLCON
        LDR     r1, =0x00010300 | (UPLL_FREQ - 8)           /* defined in config.h */