cpld7256.map.qmsg

CPLD7256的例子程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 21 16:41:03 2005 " "Info: Processing started: Mon Nov 21 16:41:03 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off cpld7256 -c cpld7256 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off cpld7256 -c cpld7256" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cpld7256.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cpld7256.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cpld7256-arch " "Info: Found design unit 1: cpld7256-arch" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "cpld7256-arch" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 cpld7256 " "Info: Found entity 1: cpld7256" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "cpld7256" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "wr cpld7256.vhd(93) " "Warning: VHDL Process Statement warning at cpld7256.vhd(93): signal or variable wr may not be assigned a new value in every possible path through the Process Statement. Signal or variable wr holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 93 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "wren cpld7256.vhd(93) " "Warning: VHDL Process Statement warning at cpld7256.vhd(93): signal or variable wren may not be assigned a new value in every possible path through the Process Statement. Signal or variable wren holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 93 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "rd cpld7256.vhd(93) " "Warning: VHDL Process Statement warning at cpld7256.vhd(93): signal or variable rd may not be assigned a new value in every possible path through the Process Statement. Signal or variable rd holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 93 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "rden cpld7256.vhd(93) " "Warning: VHDL Process Statement warning at cpld7256.vhd(93): signal or variable rden may not be assigned a new value in every possible path through the Process Statement. Signal or variable rden holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 93 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "decode2.vhd 2 1 " "Info: Using design file decode2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decode2-SYN " "Info: Found design unit 1: decode2-SYN" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/decode2.vhd" "decode2-SYN" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/decode2.vhd" 58 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 decode2 " "Info: Found entity 1: decode2" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/decode2.vhd" "decode2" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/decode2.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/quartus41/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus41/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "c:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf" "lpm_decode" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf" 67 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_3kb.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_3kb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_3kb " "Info: Found entity 1: decode_3kb" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/decode_3kb.tdf" "decode_3kb" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/decode_3kb.tdf" 28 1 0 } }  } 0}  } {  } 0}