cpld7256.tan.qmsg

CPLD7256的例子程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 21 16:41:12 2005 " "Info: Processing started: Mon Nov 21 16:41:12 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off cpld7256 -c cpld7256 " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off cpld7256 -c cpld7256" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "as wren 25.100 ns Longest " "Info: Longest tpd from source pin as to destination pin wren is 25.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns as 1 PIN PIN_97 35 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_97; Fanout = 35; PIN Node = 'as'" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "" { as } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.700 ns) + CELL(4.000 ns) 8.900 ns byte~9 2 COMB LC73 20 " "Info: 2: + IC(3.700 ns) + CELL(4.000 ns) = 8.900 ns; Loc. = LC73; Fanout = 20; COMB Node = 'byte~9'" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "7.700 ns" { as byte~9 } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(4.000 ns) 16.300 ns wr\$latch~12 3 COMB LC77 4 " "Info: 3: + IC(3.400 ns) + CELL(4.000 ns) = 16.300 ns; Loc. = LC77; Fanout = 4; COMB Node = 'wr\$latch~12'" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "7.400 ns" { byte~9 wr$latch~12 } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 93 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 23.500 ns wr\$latch~14 4 COMB LC75 1 " "Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 23.500 ns; Loc. = LC75; Fanout = 1; COMB Node = 'wr\$latch~14'" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "7.200 ns" { wr$latch~12 wr$latch~14 } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 93 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 25.100 ns wren 5 PIN PIN_134 0 " "Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 25.100 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'wren'" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "1.600 ns" { wr$latch~14 wren } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 14 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.800 ns 58.96 % " "Info: Total cell delay = 14.800 ns ( 58.96 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.300 ns 41.04 % " "Info: Total interconnect delay = 10.300 ns ( 41.04 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "25.100 ns" { as byte~9 wr$latch~12 wr$latch~14 wren } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "d\[15\] output\[15\] 10.000 ns Shortest " "Info: Shortest tpd from source pin d\[15\] to destination pin output\[15\] is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d\[15\] 1 PIN PIN_106 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_106; Fanout = 1; PIN Node = 'd\[15\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "" { d[15] } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns d\[15\]~0 2 COMB IO193 2 " "Info: 2: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = IO193; Fanout = 2; COMB Node = 'd\[15\]~0'" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "1.200 ns" { d[15] d[15]~0 } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 8.400 ns latch16:out1_latch\|lpm_latch:lpm_latch_component\|latches\[15\]~130 3 COMB LC115 3 " "Info: 3: + IC(3.200 ns) + CELL(4.000 ns) = 8.400 ns; Loc. = LC115; Fanout = 3; COMB Node = 'latch16:out1_latch\|lpm_latch:lpm_latch_component\|latches\[15\]~130'" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "7.200 ns" { d[15]~0 latch16:out1_latch|lpm_latch:lpm_latch_component|latches[15]~130 } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/lpm_latch.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_latch.tdf" 57 10 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 10.000 ns output\[15\] 4 PIN PIN_54 0 " "Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 10.000 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'output\[15\]'" {  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "1.600 ns" { latch16:out1_latch|lpm_latch:lpm_latch_component|latches[15]~130 output[15] } "NODE_NAME" } } } { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" "" "" { Text "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.800 ns 68.00 % " "Info: Total cell delay = 6.800 ns ( 68.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns 32.00 % " "Info: Total interconnect delay = 3.200 ns ( 32.00 % )" {  } {  } 0}  } { { "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" "" "" { Report "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256_cmp.qrpt" Compiler "cpld7256" "UNKNOWN" "V1" "C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/cpld7256.quartus_db" { Floorplan "" "" "10.000 ns" { d[15] d[15]~0 latch16:out1_latch|lpm_latch:lpm_latch_component|latches[15]~130 output[15] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 21 16:41:12 2005 " "Info: Processing ended: Mon Nov 21 16:41:12 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}