cpld7256.map.rpt

CPLD7256的例子程序

;       |lpm_latch:lpm_latch_component| ; 16         ; 0    ; |cpld7256|latch16:out1_latch|lpm_latch:lpm_latch_component ;
;    |latch8:out2_latch|                ; 8          ; 0    ; |cpld7256|latch8:out2_latch                                ;
;       |lpm_latch:lpm_latch_component| ; 8          ; 0    ; |cpld7256|latch8:out2_latch|lpm_latch:lpm_latch_component  ;
+---------------------------------------+------------+------+------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/cpld7256.map.eqn.


+----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                             ;
+----------------------------------------------------------------------------------+-----------------+
; File Name                                                                        ; Used in Netlist ;
+----------------------------------------------------------------------------------+-----------------+
; cpld7256.vhd                                                                     ; yes             ;
; C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/decode2.vhd       ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_decode.tdf                       ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/declut.inc                           ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_constant.inc                     ; yes             ;
; C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/db/decode_3kb.tdf ; yes             ;
; C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/latch16.vhd       ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_latch.tdf                        ; yes             ;
; C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/latch8.vhd        ; yes             ;
; C:/Documents and Settings/Administrator/桌面/乔老师io/cpld7256/bustri16.vhd      ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_bustri.tdf                       ; yes             ;
+----------------------------------------------------------------------------------+-----------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 48                   ;
; Total registers      ; 0                    ;
; I/O pins             ; 108                  ;
; Shareable expanders  ; 3                    ;
; Maximum fan-out node ; va[2]                ;
; Maximum fan-out      ; 45                   ;
; Total fan-out        ; 445                  ;
; Average fan-out      ; 2.80                 ;
+----------------------+----------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Mon Nov 21 16:41:03 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off cpld7256 -c cpld7256
Info: Found 2 design units, including 1 entities, in source file cpld7256.vhd
    Info: Found design unit 1: cpld7256-arch
    Info: Found entity 1: cpld7256
Warning: VHDL Process Statement warning at cpld7256.vhd(93): signal or variable wr may not be assigned a new value in every possible path through the Process Statement. Signal or variable wr holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at cpld7256.vhd(93): signal or variable wren may not be assigned a new value in every possible path through the Process Statement. Signal or variable wren holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at cpld7256.vhd(93): signal or variable rd may not be assigned a new value in every possible path through the Process Statement. Signal or variable rd holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: VHDL Process Statement warning at cpld7256.vhd(93): signal or variable rden may not be assigned a new value in every possible path through the Process Statement. Signal or variable rden holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Using design file decode2.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: decode2-SYN
    Info: Found entity 1: decode2
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus41/libraries/megafunctions/lpm_decode.tdf
    Info: Found entity 1: lpm_decode
Info: Found 1 design units, including 1 entities, in source file db/decode_3kb.tdf
    Info: Found entity 1: decode_3kb
Info: Using design file latch16.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: latch16-SYN
    Info: Found entity 1: latch16
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus41/libraries/megafunctions/lpm_latch.tdf
    Info: Found entity 1: lpm_latch
Info: Using design file latch8.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: latch8-SYN
    Info: Found entity 1: latch8
Info: Using design file bustri16.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: bustri16-SYN
    Info: Found entity 1: bustri16
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/quartus41/libraries/megafunctions/lpm_bustri.tdf
    Info: Found entity 1: lpm_bustri
Warning: Output pins are stuck at VCC or GND
    Warning: Pin dtack stuck at VCC
Warning: Design contains 22 input pin(s) that do not drive logic
    Warning: No output dependent on input pin va[23]
    Warning: No output dependent on input pin va[22]
    Warning: No output dependent on input pin va[21]
    Warning: No output dependent on input pin va[20]
    Warning: No output dependent on input pin va[19]
    Warning: No output dependent on input pin va[15]
    Warning: No output dependent on input pin va[14]
    Warning: No output dependent on input pin va[13]
    Warning: No output dependent on input pin va[12]
    Warning: No output dependent on input pin va[11]
    Warning: No output dependent on input pin va[10]
    Warning: No output dependent on input pin va[9]
    Warning: No output dependent on input pin va[8]
    Warning: No output dependent on input pin va[7]
    Warning: No output dependent on input pin va[6]
    Warning: No output dependent on input pin va[5]
    Warning: No output dependent on input pin va[4]
    Warning: No output dependent on input pin va[3]
    Warning: No output dependent on input pin sysrst
    Warning: No output dependent on input pin lword
    Warning: No output dependent on input pin ds1
    Warning: No output dependent on input pin ds0
Info: Implemented 159 device resources after synthesis - the final resource count might be different
    Info: Implemented 61 input pins
    Info: Implemented 31 output pins
    Info: Implemented 16 bidirectional pins
    Info: Implemented 48 macrocells
    Info: Implemented 3 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 29 warnings
    Info: Processing ended: Mon Nov 21 16:41:06 2005
    Info: Elapsed time: 00:00:03