cpld7256.vhd

CPLD7256的例子程序

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY cpld7256 IS
	PORT (
		  input : in  std_logic_vector(31 downto 0);
		  output : out  std_logic_vector(23 downto 0);
		  va : in  std_logic_vector(23 downto 1);
		  d : inout  std_logic_vector(15 downto 0);
		  
		  dtack: out  std_logic;
          sysrst,lword,w_r,as,ds1,ds0: in std_logic;

          rd,rden,wr,wren,byte,my:out  std_logic
         );
END cpld7256;

ARCHITECTURE arch OF cpld7256 IS

signal decodeout: std_logic_vector(3 downto 0);

component decode2
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
		enable		: IN STD_LOGIC ;
		eq0		: OUT STD_LOGIC ;
		eq1		: OUT STD_LOGIC ;
		eq2		: OUT STD_LOGIC ;
		eq3		: OUT STD_LOGIC 
	);
end component;
component latch16	
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		gate		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
end component;
component latch8	
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		gate		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
end component;

component bustri16
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		enabledt	: IN STD_LOGIC ;
		tridata		: INOUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
end component;

BEGIN
    my <= as or (not((not va(18)) and (not va(17)) and va(16)));
	byte <= as or (not((not va(18)) and (not va(17)) and va(16)));
	dtack <= '1';
addr_decode : decode2 PORT MAP (
		data	 => va(2 downto 1),
		enable	 => not (as or (not((not va(18)) and (not va(17)) and va(16)))),
		eq0	 => decodeout(0),
		eq1	 => decodeout(1),
		eq2	 => decodeout(2),
		eq3	 => decodeout(3)
	);

out1_latch : latch16 PORT MAP (
		data	 => d,
		gate	 => not w_r and decodeout(2),
		q	 => output(15 downto 0)
	);
out2_latch : latch8 PORT MAP (
		data	 => d(7 downto 0),
		gate	 => not w_r and decodeout(3),
		q	 => output(23 downto 16)
	);

in1_tri : bustri16 PORT MAP (
		data	 => input(15 downto 0),
		enabledt =>  w_r and decodeout(0),
		tridata	 => d
	);
in2_tri : bustri16 PORT MAP (
		data	 => input(31 downto 16),
		enabledt =>  w_r and decodeout(1),
		tridata	 => d
	);
p1:process (decodeout)
   begin 
	   if(decodeout(2)='1' or decodeout(3)='1') then
	       wr<='0';
	       wren<='0';
	       rd<='1';
	       rden<='1';
	
	   end if;
	   if(decodeout(0)='1' or decodeout(1)='1') then
	       rd<='0';
	       rden<='0';
	       wr<='1';
	       wren<='1';
	
	   end if;
 end process p1;
END arch;