16b.h

MSC1210单片机在TINY操作系统下的C语言例程

/*
HIRFL magnatice power adjust controller is based msc1210 device.
This file define It's inside register and bus device, also define
program data structure and etc.
*/
#define uint  unsigned int
#define uchar unsigned char

#define SET		1
#define CLEAR 	0
#define TRUE	1
#define FALSE	0

/*
define task name used programming.You can add some task to Here. 
*/
#define INIT      		0               /* 系统初始化任务         */
#define LOGIC_JUDGE     1              
  
//******************************************************************************************

/*
define frequency of main osillate.  
*/
#define IFCONFIG_FOSC_11M
//#define IFCONFIG_FOSC_33M


/*
Clock (fosc)control REG CKCON define.
This bit is 0 The F=fosc/12, 1 is F=fosc/4
*/
#ifdef IFCONFIG_FOSC_11M
#define T1M  (1 << 3) 		/* Timer 1 */
#endif
#ifdef IFCONFIG_FOSC_33M
#define T1M  0 				/* Timer 1 */
#endif
#define T0M  (1 << 4) 		/* Timer 0 */
#define T2M  (1 << 5) 		/* Timer 2 */
#define MD0  1 	 			/* Timer 0 */
#define MD1  (1 << 1) 		/* Timer 1 */
#define MD2  (1 << 2) 		/* Timer 2 */


/*
serial Port define.
*/
#define SMOD 	(1 << 7)		/* PCON.7 This bit is 0 The F=fosc/64, 1 is F=fosc/32 */
#define SMOD_2_MOD0	0			/* SCON1.7_6_5 This bits are 000 synchronitic */
#define MOD1 	(2 << 5)		/* SCON.7_6_5 This bits are 010 A mode 1 */
#define MOD3 	(6 << 5)		/* SCON.7_6_5 This bits are 110 A mode 3 */
#define RENN 	(1 << 4)		/* SCON.4 This bit is 1 The Receive Enable */
#define TIN  	(1 << 1)		/* SCON.1 This bit is 1 The transfer INT Status */
#define TMOD_M 	(2 << 4)		/* TMOD.5_4 This bit are 10 The mode 2 */
#ifdef IFCONFIG_FOSC_11M	/* Baudrate to TH1 */
#define TH57600    0xFF	
#define TH19200    0xFD
#define TH9600     0xFA
#define TH4800     0xF4
#define TH2400     0xE8
#define TH1200     0xD0
#endif
#ifdef IFCONFIG_FOSC_33M	/* Baudrate to TH1 */
#define TH57600    	0xF7
#define TH19200    	0xE5
#define TH9600    	0xCA
#define TH4800    	0x94
#define TH2400    	0x28
#endif
/*
WatchDog set
*/
#define EWDT  	(1 << 7)		/*WDTCON.7 Enable set */
#define RWDT  	(1 << 5)		/*WDTCON.5 recount */


/*
SPI control REG define.(frame is 8Baty,once 8 SCLK)
*/
/* PDCON */
#define PDWDT  	(1 << 2)		/*PDCON.2 This is 1 turn on Watchdog,0 is turn off */
#define PDSPI  	1				/*PDCON.0 This is 1 turn off SPI,0 is turn on */
#define PDST  	(1 << 1)		/*PDCON.1 This is 1 turn off ST,0 is turn on */
#define PDAD  	(1 << 3)		/*PDCON.3 This is 1 turn off ADC,0 is turn on */
#define PDPWM  	(1 << 4)		/*PDCON.4 This is 1 turn off PWM,0 is turn on */


/* SPITCON */
#define SCLK_EN	(1 << 5)		/* SPITCON.5 This is 1 SCLK Enable */
#define DRV_EN	(1 << 3)		/* SPITCON.3 This is 1 Driver Enable */
#define ORDER	(1 << 3)		/* SPICON.3 This is 1 The LSB at the first,0 is the MSB at the first */
#define MSTR	(1 << 2)		/* SPICON.2 This is 1 The main mode, 0 is Aux mode */
#define CPHA	(1 << 1)		/* SPICON.1 This is 1 The data begin from the first SCLK */
#define CPOL     1				/* SPICON.1 This is 1 xiang wei*/

#ifdef IFCONFIG_FOSC_11M	                     /* Fosc is 11MHz */
#define SCLK_8532	        0			/* SPICON.7_6_5 This are 0 fosc/2 */
#define SPICON_8532		    SCLK_8532|MSTR|CPHA
#define SPICON_25256		SCLK_8532|MSTR|CPHA|CPOL
#endif

#ifdef IFCONFIG_FOSC_33M	                     /* Fosc is 33MHz  */
#define SCLK_8532	       (1 << 5)		         /* SPICON.7_6_5 This are 001 fosc/4 */
#define SPICON_8532		   SCLK_8532|MSTR|CPHA
#define SPICON_25256	   SCLK_8532|MSTR|CPHA|CPOL
#endif

	/* fm25l256 Operation */
#define WREN_INST  0X06    /*set write enable latch*/
#define WRDI_INST  0X04    /*write disable */
#define WRSR_INST  0X01    /*write status register*/
#define RDSR_INST  0X05    /*read status register*/
#define WRITE_INST 0X02    /*write memory data */
#define READ_INST  0X03    /*read memory data */ 


/*DAC8532 Modes Operation 
*/
#define MOD_NORM	0                  /*DB.17_16(PD1 PD0) is 00 Normal Operation*/
#define MOD_1		1                  /*DB.17_16(PD1 PD0) is 01 Output 1kΩ to GND*/
#define MOD_2		( 1 << 1 )         /*DB.17_16(PD1 PD0) is 10 Output 100kΩ to GND*/
#define MOD_3		3		           /*DB.17_16(PD1 PD0) is 11 High-Z*/
#define BS_b		( 1 << 2 )		   /*DB.18 is 1  buf_b  0 is buf_a */
#define LD_a		( 1 << 4 )		   /*DB.20 (load a ch  is 1 */
#define LD_b		( 1 << 5 )		   /*DB.21 (load b ch  is 1 */
#define Dac8532A    0x10      		   /*Normal Operation A passage*/
#define Dac8532B    0x24			   /*Normal Operation B passage*/

/*
adc control REG define.(frame is 8Baty,once 8 SCLK)
*/
#define AD_EN	(1 << 5)		/* AIE.6 is 1 Enable A/D INT */
#define ESEC_EN	(1 << 7)		/* AIE.7 is 1 Enable second timer INT */
#define SECC	(1 << 7)		/* AISTAT.7 is 1 second timer INT */
#define EMSEC	(1 << 4)		/* AISTAT.4 is 1 ms timer INT */
#define ESPIR   (1 << 2)		/* AIE.2 is 1 Enable SPIRX  INT */


#define INP_0	0	        	/* ADMUX.7_6_5_4 This is 0000 The AIN0 is + input */
#define INP_1	(1 << 4)		/* ADMUX.7_6_5_4 This is 0001 The AIN1 is + input */
#define INP_2	(1 << 5)		/* ADMUX.7_6_5_4 This is 0010 The AIN2 is + input */
#define INP_3	(3 << 4)		/* ADMUX.7_6_5_4 This is 0011 The AIN3 is + input */
#define INP_4	(1 << 6)		/* ADMUX.7_6_5_4 This is 0100 The AIN4 is + input */
#define INP_5	(5 << 4)		/* ADMUX.7_6_5_4 This is 0101 The AIN5 is + input */
#define INP_6	(3 << 5)		/* ADMUX.7_6_5_4 This is 0110 The AIN6 is + input */
#define INP_7	(7 << 4)		/* ADMUX.7_6_5_4 This is 0111 The AIN7 is + input */
#define INP_COM	(1 << 7)		/* ADMUX.7_6_5_4 This is 1000 The AINCOM is + input */

#define INN_0	0     		/* ADMUX.3_2_1_0 This is 0000 The AIN0 is - input */
#define INN_1	1     		/* ADMUX.3_2_1_0 This is 0001 The AIN1 is - input */
#define INN_2	(1 << 1) 	/* ADMUX.3_2_1_0 This is 0010 The AIN2 is - input */
#define INN_3	3     		/* ADMUX.3_2_1_0 This is 0011 The AIN3 is - input */
#define INN_4	(1 << 2) 	/* ADMUX.3_2_1_0 This is 0100 The AIN4 is - input */
#define INN_5	5     		/* ADMUX.3_2_1_0 This is 0101 The AIN5 is - input */
#define INN_6	(3 << 1)    /* ADMUX.3_2_1_0 This is 0110 The AIN6 is - input */
#define INN_7	7     		/* ADMUX.3_2_1_0 This is 0111 The AIN7 is - input */
#define INN_COM	(1 << 3) 	/* ADMUX.3_2_1_0 This is 1000 The AINCOM is - input */

#define BOD		(1 << 6)    /* ADCON0.6 This is 1 The turn on input current,0 is turn off */
#define EVREF	(1 << 5)   	/* ADCON0.5 This is 1 The turn on VREF,0 is turn off */
#define VREFH	(1 << 4)  	/* ADCON0.4 This is 1 The VREF 2.5V,0 is 1.25V */
#define EBUF	(1 << 3) 	/* ADCON0.3 This is 1 The Buffer Enable,0 is disable */
#define PGA_1	0         	/* ADCON0.2_1_0 This is 000 The PGA is 1 */
#define PGA_2	1         	/* ADCON0.2_1_0 This is 001 The PGA is 2 */
#define PGA_4	(1 << 1)    /* ADCON0.2_1_0 This is 010 The PGA is 4 */
#define PGA_8	3         	/* ADCON0.2_1_0 This is 011 The PGA is 8 */
#define PGA_16	(1 << 2)    /* ADCON0.2_1_0 This is 100 The PGA is 16 */
#define PGA_32	5         	/* ADCON0.2_1_0 This is 101 The PGA is 32 */
#define PGA_64	(3 << 1)    /* ADCON0.2_1_0 This is 110 The PGA is 64 */
#define PGA_128	7         	/* ADCON0.2_1_0 This is 111 The PGA is 128 */

#define POL		(1 << 6)    /* ADCON1.6 This is 1 The Unipolar,0 is bipolar */
#define SM_0	0          	/* ADCON1.5_4 This is 00 The auto filter */
#define SM_1	(1 << 4)    /* ADCON1.5_4 This is 01 The fast stable filter */
#define SM_2	(1 << 5)    /* ADCON1.5_4 This is 10 The Sinc2 filter */
#define SM_3	(3 << 4)    /* ADCON1.5_4 This is 11 The Sinc3 filter */
#define CAL_0	0         	/* ADCON1.2_1_0 This is 000 The No adjust */
#define CAL_1	1         	/* ADCON1.2_1_0 This is 001 The excursion and plus  self adjust */
#define CAL_2	(1 << 1)    /* ADCON1.2_1_0 This is 010 The excursion self adjust */
#define CAL_3	3         	/* ADCON1.2_1_0 This is 011 The plus  self adjust */
#define CAL_4	(1 << 2)    /* ADCON1.2_1_0 This is 100 The excursion system adjust */
#define CAL_5	5         	/* ADCON1.2_1_0 This is 101 The plus system adjust */

#define SSCON_0		0          	/* SSCON.7_6 This is 00 The CPU is data source ,mode 0 */
#define SSCON_1		(1 << 6)   	/* SSCON.7_6 This is 01 The ADC is data source ,mode 1 */
#define SSCON_2		(1 << 7)   	/* SSCON.7_6 This is 10 The CPU is data source ,mode 2 */
#define SSCON_3		(3 << 6)   	/* SSCON.7_6 This is 11 The ADC is data source ,mode 3 */
#define SCNT_2		0          	/* SSCON.5_4_3 This is 000 The add time is 2 */
#define SCNT_4		(1 << 3)    /* SSCON.5_4_3 This is 001 The add time is 4 */
#define SCNT_8		(1 << 4)    /* SSCON.5_4_3 This is 010 The add time is 8 */
#define SCNT_16		(3 << 3)   	/* SSCON.5_4_3 This is 011 The add time is 16 */
#define SCNT_32		(1 << 5)   	/* SSCON.5_4_3 This is 100 The add time is 32 */
#define SCNT_64		(5 << 3)   	/* SSCON.5_4_3 This is 101 The add time is 64 */
#define SCNT_128	(3 << 4)  	/* SSCON.5_4_3 This is 110 The add time is 128 */
#define SCNT_256	(7 << 3)  	/* SSCON.5_4_3 This is 111 The add time is 256 */
#define SHF_1		0          	/* SSCON.2_1_0 This is 000 The move 1 bit */
#define SHF_2		1          	/* SSCON.2_1_0 This is 001 The move 2 bit */
#define SHF_3		(1 << 1)    /* SSCON.2_1_0 This is 010 The move 3 bit */
#define SHF_4		3          	/* SSCON.2_1_0 This is 011 The move 4 bit */
#define SHF_5		(1 << 2)    /* SSCON.2_1_0 This is 100 The move 5 bit */
#define SHF_6		5          	/* SSCON.2_1_0 This is 101 The move 6 bit */
#define SHF_7		(3 << 1)    /* SSCON.2_1_0 This is 110 The move 7 bit */
#define SHF_8		7          	/* SSCON.2_1_0 This is 111 The move 8 bit */

typedef char BUS_REG;

#define W_ADDRESS                      ((int xdata*)      0xe000)

/*
define ADC ring buffer struct type
*/
typedef struct _adbuf
{
	unsigned int buf[8];                 	/*ADC buffer*/
	unsigned char ps;                  		/*analog channel*/
} xdata adbuf;

adbuf adcsum ;


extern signed long unipolar();