rsnand.vhd

来自「《CPLD/FPGA嵌入式应用开发技术白金手册》源代码」· VHDL 代码 · 共 23 行

--RSNAND
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity rsnand is 
port(r_in:in std_logic;
	 s_in:in std_logic;
	 q_out:out std_logic);
end rsnand;
 --rsnand
architecture behave of rsnand is
signal r_temp:std_logic;
signal s_temp:std_logic;
begin
   q_out<=not(r_in and s_temp);
   r_temp<=not(r_in and s_temp);
   s_temp<=not(s_in and r_temp);
end behave;