disp.vhd

《CPLD/FPGA嵌入式应用开发技术白金手册》源代码

--数据显示子模块，自带分频，6位动态显示
package test_con is
	constant N1:integer:=3686;
	constant N2:integer:=10;
end test_con;
use work.test_con.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity disp is
port (key1:in std_logic;
	clk:in std_logic;
	des1,des2,des3,des4,des5,des6:in std_logic_vector(7 downto 0);
	--state:in std_logic;
	data1:buffer std_logic_vector(7 downto 0);
	data2:buffer std_logic_vector(5 downto 0));
end disp;
architecture rtl of disp is
signal temp,temp2,clk1,clk2:std_logic;
signal sig_data2:std_logic_vector(5 downto 0);
component fredivn
	generic(N:positive);
	port (clk:in std_logic;
		outclk:out std_logic);
END component;

begin
u1:fredivn
	generic map(N=>N1)
	port map(clk,clk1);
u2:fredivn
	generic map(N=>N2)
	port map(clk,clk2);

process(clk2)
--variable temp:std_logic_vector(3 downto 0):="1111";

begin
if(clk2'event and clk2='1')then
	if temp='1' then
		temp2<=sig_data2(5);
		for i in 5 downto 1 loop
			sig_data2(i)<=sig_data2(i-1);
		end loop;
		sig_data2(0)<=temp2;
	else
		sig_data2<="000001";
	end if;
end if;
end process;

process(key1)
begin
if(key1'event and key1='0')then
temp<=not temp;

end if;
end process;
process(clk2)
begin
if(clk2'event and clk2='1')then
	if temp='1' then
				data2<=sig_data2;
	else
				data2<="000000";
	end if;
end if;
end process;
process
begin
case data2 is
			when "000001"=>data1<=des1;
			when "000010"=>data1<=des2;
			when "000100"=>data1<=des3;
			when "001000"=>data1<=des4;
			when "010000"=>data1<=des5;
			when "100000"=>data1<=des6;
			when others =>data1<="00000000";
end case;

end process;
end rtl;